Datasheet

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MT9D111__6_REV5.fm - Rev. B 2/06 EN
119 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Sensor Core
Micron Confidential and Proprietary
Raw Data Timing
The sensor core output data is synchronized with the PIXCLK output. When
LINE_VALID is HIGH, one pixel datum is output on the 10-bit D
OUT output every PIX-
CLK period. By default, the PIXCLK signal runs at the same frequency as the master
clock, and its rising edges occur one-half of a master clock period after transitions on
LINE_VALID, FRAME_VALID, and D
OUT (see Figure 18). This allows PIXCLK to be used as
a clock to sample the data. PIXCLK is continuously enabled, even during the blanking
period. The sensor core can be programmed to delay the PIXCLK edge relative to the
D
OUT transitions from 0 to 3.5 master clocks, in steps of one-half of a master clock. This
can be achieved by programming the corresponding bits in R0x0A:0. The parameters P,
A, and Q in Figure 19 are defined in Table 27 on page 120.
Figure 18: Pixel Data Timing Example
Figure 19: Row Timing and FRAME_VALID/LINE_VALID Signals
The sensor timing is shown in terms of pixel clock and master clock cycles (see Figure 18
on page 119). The recommended master clock frequency is 36 MHz. Increasing the inte-
gration time to more than one frame causes the frame time to be extended. The equa-
tions in Table assume integration time is less than the number of rows in a frame
(R0x09:0 < R0x03:0/S + BORDER + VBLANK_REG). If this is not the case, the number of
integration rows must be used instead to determine the frame time, as shown in
Tab le 2 8.
P
0
(9:0)
P
1
(9:0)
P
2
(9:0)
P
3
(9:0)
P
4
(9:0)
P
n-1
(9:0)
P
n
(9:0)
Valid Image DataBlanking Blanking
LINE_VALID
PIXCLK
D
OUT0-DOUT9
FRAME_VALID
LINE_VALID
Number of master clocks
PAQ AQAP