Datasheet

PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__6_REV5.fm - Rev. B 2/06 EN
116 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Sensor Core
Micron Confidential and Proprietary
Sensor Core
This section describes the sensor core. The core is based entirely on Micron’s MT9D011
sensor.
The SOC firmware controls a key sensor core registers, such as exposure, window size,
gains, and contexts. When firmware or MCU are disabled, the sensor core can be pro-
grammed directly.
Introduction
The sensor core is a progressive-scan sensor that generates a stream of pixel data quali-
fied by LINE_VALID and FRAME_VALID signals. An on-chip PLL generates the master
clock from an input clock of 6 MHz to 40 MHz. In default mode, the data rate (pixel
clock) is the same as the master clock frequency, which means that one pixel is gener-
ated every master clock cycle. The sensor block diagram is shown in Figure 13.
Figure 13: Sensor Core Block Diagram
The core of the sensor is an active-pixel array. The timing and control circuitry
sequences through the rows of the array, resetting and then reading each row. In the time
interval between resetting a row and reading that row, the pixels in that row integrate
incident light. The exposure is controlled by varying the time interval between reset and
readout. After a row is read, the data from the columns is sequenced through an analog
signal chain (providing offset correction and gain), and then through an ADC. The out-
put from the ADC is a 10-bit value for each pixel in the array. The pixel array contains
optically active and light-shielded “black” pixels. The black pixels are used to provide
data for on-chip offset correction algorithms (black level control).
The sensor contains a set of 16-bit control and status registers that can be used to con-
trol many aspects of the sensor operations. These registers can be accessed through a
two-wire serial interface. In this document, registers are specified either by name (Col-
umn Start) or by register address (R0x04:0). Fields within a register are specified by bit or
by bit range (R0x20:0[0] or R0x0B:0[13
:0]). The control and status registers are described
in Table 5, "Sensor Register Description," on page 29.
The output from the sensor is a Bayer pattern: alternate rows are a sequence of either
green/red pixels or blue/green pixels. The offset and gain stages of the analog signal
chain provide per-color control of the pixel data.
Active-Pixel Sensor
(APS) Array
UXGA
1600H x 1200V
Serial
I/O
Data
Out
Sync
Signals
Control Register
Analog Processing ADC
Timing and Control