Datasheet
Table Of Contents
- 1/3.2-Inch System-On-A-Chip (SOC) CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- General Description
- Feature Overview
- Typical Connection
- Ballout and Interface
- Architecture Overview
- Registers and Variables
- Registers
- Registers
- IFP Registers, Page 1
- IFP Registers, Page 2
- JPEG Indirect Registers
- Table 8: JPEG Indirect Registers (See Registers 30 and 31, Page 2)
- Firmware Driver Variables
- Table 9: Drivers IDs
- Table 10: Driver Variables-Monitor Driver (ID = 0)
- Table 11: Driver Variables-Sequencer Driver (ID = 1)
- Table 12: Driver Variables-Auto Exposure Driver (ID = 2)
- Table 13: Driver Variables-Auto White Balance (ID = 3)
- Table 14: Driver Variables-Flicker Detection Driver (ID = 4)
- Table 15: Driver Variables-Auto Focus Driver (ID = 5)
- Table 16: Driver Variables-Auto Focus Mechanics Driver (ID = 6)
- Table 17: Driver Variables-Mode/Context Driver (ID = 7)
- Table 18: Driver Variables-JPEG Driver (ID = 9)
- Table 19: Driver Variables-Histogram Driver (ID = 11)
- MCU Register List and Memory Map
- JPEG Indirect Registers
- Output Format and Timing
- Sensor Core
- Feature Description
- PLL Generated Master Clock
- PLL Setup
- Window Control
- Pixel Border
- Readout Modes
- Figure 20: 6 Pixels in Normal and Column Mirror Readout Modes
- Figure 21: 6 Rows in Normal and Row Mirror Readout Modes
- Table 30: Skip Values
- Figure 22: 8 Pixels in Normal and Column Skip 2x Readout Modes
- Figure 23: 16 Pixels in Normal and Column Skip 4x Readout Modes
- Figure 24: 32 Pixels in Normal and Column Skip 8x Readout Modes
- Figure 25: 64 Pixels in Normal and Column Skip 16x Readout Modes
- Table 31: Row Addressing
- Table 32: Column Addressing
- Frame Rate Control
- Context Switching
- Integration Time
- Flash STROBE
- Global Reset
- Analog Signal Path
- Analog Inputs AIN1-AIN3
- Firmware
- Firmware
- Start-Up and Usage
- General Purpose I/O
- Introduction
- GPIO Output Control Overview
- Waveform Programming
- Notification Signals
- Digital and Analog Inputs
- GPIO Software Drivers
- Auto Focus
- Figure 42: Search for Best Focus
- Figure 43: Scene with Two Potential Focus Targets at Different Distances from Camera
- Figure 44: Dependence of Luminance-Normalized Local Sharpness Scores on Lens Position
- Figure 45: Example of Position Weight Histogram Created by AF Driver
- Figure 46: Auto Focus Windows
- Figure 47: Computation of Sharpness Scores and Luminance Average for an AF Window
- Table 41: Examples of AF Filters that can be Programmed into the MT9D111
- Spectral Characteristics
- Electrical Specifications
- Packaging
- Appendix A: Two-Wire Serial Register Interface
- Protocol
- Sequence
- Bus Idle State
- Start Bit
- Stop Bit
- Slave Address
- Data Bit Transfer
- Acknowledge Bit
- No-Acknowledge Bit
- Page Register
- Sample Write and Read Sequences
- Figure 52: WRITE Timing to R0x09:0-Value 0x0284
- Figure 53: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 54: WRITE Timing to R0x09:0-Value 0x0284
- Figure 55: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 56: Two-Wire Serial Bus Timing Parameters
- Table 46: Two-wire Serial Bus Characteristics
- Revision History
PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__6_REV5.fm - Rev. B 2/06 EN
113 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Output Format and Timing
Micron Confidential and Proprietary
The "continuous" and spoof JPEG output modes differ primarily in how the LINE_VALID
output is asserted. In the continuous mode, LINE_VALID is asserted only during output
clock cycles containing valid JPEG data. The resulting LINE_VALID signal pattern is non-
uniform and highly image dependent, reflecting the inherent nature of JPEG data
stream. In the spoof mode, LINE_VALID is asserted and de-asserted in a more uniform
pattern emulating uncompressed video output with horizontal blanking intervals. When
LINE_VALID is de-asserted, available JPEG data are not output, but instead remain in
the FIFO until LINE_VALID is asserted again. During the time when LINE_VALID is
asserted, the output clock is gated off whenever there is no valid JPEG data in the FIFO.
Note: As a result, spoof “lines” containing the same number of valid data bytes may be out-
put within different time intervals depending on constantly varying JPEG data rate.
The host processor configures the spoof pattern by programming the total number of
LINE_VALID assertion intervals, as well as the number of output clock periods during
and between LINE_VALID assertions. In other words, the host processor can define a
temporal “frame” for JPEG output, preferably with “size” tailored to the expected JPEG
file size. If this frame is too large for the total number of JPEG bytes actually produced,
the MT9D111 either de-asserts FRAME_VALID or continues to pad unused “lines” with
zeros until the end of the frame. If the frame is too small, the MT9D111 either continues
to output the excess JPEG bytes until the entire JPEG compressed image is output or dis-
cards the excess JPEG bytes and sets an error flag in a status register accessible to the
host processor.
In the continuous output mode, the JPEG output clock can be configured to be either
gated off or running while LINE_VALID is de-asserted. To save extra power, the JPEG out-
put clock can also be gated off between frames (when FRAME_VALID is de-asserted) in
both continuous and spoof output mode. In the continuous output mode, there is an
option to insert JPEG SOI (0xFFD8) and EOI (0xFFD9) markers respectively before and
after valid JPEG data. SOI and EOI can be inserted either inside or outside the
FRAME_VALID assertion period, but always outside LINE_VALID assertions.
The output order of even and odd bytes of JPEG data can be swapped in the spoof output
mode. This option is not supported in the continuous mode.
Output clock speed can optionally be made to vary according to the fullness of the FIFO,
to reduce the likelihood of FIFO overflow. When this option is enabled, the output clock
switches at three fixed levels of FIFO fullness (25 percent, 50 percent and 75 percent) to a
higher or lower frequency, depending on the direction of fullness change. The set of pos-
sible output clock frequencies is restricted by the fact that its period must be an integer
multiple of the master clock period. The frequencies to be used are chosen by program-
ming three output clock frequency divisors in registers R14:2 and R15:2. Divisor N1 is
used if the FIFO is less than 50 percent full and last fullness threshold crossed has been
25 percent. When the FIFO reaches 50 percent and 75 percent fullness, the output clock
switches to divisor N2 and N3, respectively. When the FIFO fullness level drops to 50 per-
cent and 25 percent, the output clock is switched back to divisor N2 and N1, respectively.
The host processor can read registers containing JPEG status flags and JPEG data length
(total byte count of valid JPEG data) via a two-wire serial interface. In addition, the JPEG
data length and JPEG status byte are always appended at the end of JPEG spoof frame.
JPEG status byte can be optionally appended at the end of JPEG continuous frame. JPEG
data stream sent to the host does not have a header.










