Datasheet
Table Of Contents
- 1/3.2-Inch System-On-A-Chip (SOC) CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- General Description
- Feature Overview
- Typical Connection
- Ballout and Interface
- Architecture Overview
- Registers and Variables
- Registers
- Registers
- IFP Registers, Page 1
- IFP Registers, Page 2
- JPEG Indirect Registers
- Table 8: JPEG Indirect Registers (See Registers 30 and 31, Page 2)
- Firmware Driver Variables
- Table 9: Drivers IDs
- Table 10: Driver Variables-Monitor Driver (ID = 0)
- Table 11: Driver Variables-Sequencer Driver (ID = 1)
- Table 12: Driver Variables-Auto Exposure Driver (ID = 2)
- Table 13: Driver Variables-Auto White Balance (ID = 3)
- Table 14: Driver Variables-Flicker Detection Driver (ID = 4)
- Table 15: Driver Variables-Auto Focus Driver (ID = 5)
- Table 16: Driver Variables-Auto Focus Mechanics Driver (ID = 6)
- Table 17: Driver Variables-Mode/Context Driver (ID = 7)
- Table 18: Driver Variables-JPEG Driver (ID = 9)
- Table 19: Driver Variables-Histogram Driver (ID = 11)
- MCU Register List and Memory Map
- JPEG Indirect Registers
- Output Format and Timing
- Sensor Core
- Feature Description
- PLL Generated Master Clock
- PLL Setup
- Window Control
- Pixel Border
- Readout Modes
- Figure 20: 6 Pixels in Normal and Column Mirror Readout Modes
- Figure 21: 6 Rows in Normal and Row Mirror Readout Modes
- Table 30: Skip Values
- Figure 22: 8 Pixels in Normal and Column Skip 2x Readout Modes
- Figure 23: 16 Pixels in Normal and Column Skip 4x Readout Modes
- Figure 24: 32 Pixels in Normal and Column Skip 8x Readout Modes
- Figure 25: 64 Pixels in Normal and Column Skip 16x Readout Modes
- Table 31: Row Addressing
- Table 32: Column Addressing
- Frame Rate Control
- Context Switching
- Integration Time
- Flash STROBE
- Global Reset
- Analog Signal Path
- Analog Inputs AIN1-AIN3
- Firmware
- Firmware
- Start-Up and Usage
- General Purpose I/O
- Introduction
- GPIO Output Control Overview
- Waveform Programming
- Notification Signals
- Digital and Analog Inputs
- GPIO Software Drivers
- Auto Focus
- Figure 42: Search for Best Focus
- Figure 43: Scene with Two Potential Focus Targets at Different Distances from Camera
- Figure 44: Dependence of Luminance-Normalized Local Sharpness Scores on Lens Position
- Figure 45: Example of Position Weight Histogram Created by AF Driver
- Figure 46: Auto Focus Windows
- Figure 47: Computation of Sharpness Scores and Luminance Average for an AF Window
- Table 41: Examples of AF Filters that can be Programmed into the MT9D111
- Spectral Characteristics
- Electrical Specifications
- Packaging
- Appendix A: Two-Wire Serial Register Interface
- Protocol
- Sequence
- Bus Idle State
- Start Bit
- Stop Bit
- Slave Address
- Data Bit Transfer
- Acknowledge Bit
- No-Acknowledge Bit
- Page Register
- Sample Write and Read Sequences
- Figure 52: WRITE Timing to R0x09:0-Value 0x0284
- Figure 53: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 54: WRITE Timing to R0x09:0-Value 0x0284
- Figure 55: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 56: Two-Wire Serial Bus Timing Parameters
- Table 46: Two-wire Serial Bus Characteristics
- Revision History
PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__6_REV5.fm - Rev. B 2/06 EN
112 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Output Format and Timing
Micron Confidential and Proprietary
Uncompressed 10-Bit Bypass Output
Raw 10-bit Bayer data from the sensor core can be output in bypass mode in two ways:
1. Using 10 data output pads (D
OUT0–DOUT9), or
2. Using only 8 pads (D
OUT0–DOUT7) and a special 8 + 2 data format, shown in Table 26.
The timing of 10-bit or 8-bit data stream output in the bypass mode is qualitatively the
same as that depicted in Figure 7.
Figure 9: Example of Timing for Non-Decimated Uncompressed Output Bypassing
Output FIFO
JPEG Compressed Output
JPEG compression of IFP output produces a data stream whose structure differs from
that of an uncompressed YUV/RGB stream. Frames are no longer sequences of lines of
constant length. This difference is reflected in the timing of the LINE_VALID signal.
When JPEG compression is enabled, logical HIGHs on LINE_VALID do not correspond
to image lines, but to variably sized packets of valid data. In other words, the
LINE_VALID signal is in fact a DATA_VALID signal. It is a good analogy to compare the
JPEG output of the MT9D111 to an 8-bit parallel data port wherein the LINE_VALID sig-
nal indicates valid data and the FRAME_VALID signal indicates frame timing.
The JPEG compressed data can be output either continuously or in blocks simulating
image lines. The latter output scheme is intended to spoof a standard video pixel port
connected to the MT9D111 and for that purpose treats JPEG entropy-coded segments as
if they were standard video pixels. In the continuous output mode, JPEG output clock
can be free running or gated. In all, three timing modes are available and are depicted in
Figure 10 on page 114, Figure 11 on page 114, and Figure 12 on page 114. These timing
diagrams are merely three typical examples of many variations of JPEG output. Descrip-
tion of output configuration register R13:2 in Table 7, "IFP Registers, Page 2," on page 52
provides more information on different output interface configuration options.
Table 26: 2-Byte RGB Format
Odd bytes 8 data bits D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
Even bytes 2 data bits + 6
unused bits
0 0 0 0 0 0 D
1
D
0
0xFF 0x00 0x00 0xAB 0xFF 0x00 0x00 0x80 Cb
0
Y
0
Cr
0
Y
1
Cb
0
Y
0
Cr
0
Y
1
0xFF 0x00 0x00 0x9D 0xFF 0x00 0x00 0xB6










