Datasheet

PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__6_REV5.fm - Rev. B 2/06 EN
111 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Output Format and Timing
Micron Confidential and Proprietary
Figure 8: Details of Uncompressed YUV/RGB Output Timing
Uncompressed YUV/RGB Data Ordering
The MT9D111 supports swapping YCrCb mode, as illustrated in Table 24.
The RGB output data ordering in default mode is shown in Table 25. The odd and even
bytes are swapped when luma/chroma swap is enabled. R and B channels are bit-wise
swapped when chroma swap is enabled.
Symbol Definition Conditions MIN MAX Units
f
PIXCLK
PIXCLK frequency Default 80 MHz
t
PD
PIXCLK to data valid Default -3 3 ns
t
PFH
PIXCLK to FV high Default -3 3 ns
t
PLH
PIXCLK to LV high Default -3 3 ns
t
PFL
PIXCLK to FV low Default -3 3 ns
t
PLL
PIXCLK to LV low Default -3 3 ns
Table 24: YCrCb Output Data Ordering
Mode
Default (no swap) Cb
i
Y
i
Cr
i
Y
i+1
Swapped CrCb Cr
i
Y
i
Cb
i
Y
i+1
Swapped YC Y
i
Cb
i
Y
i+1
Cr
i
Swapped CrCb, YC Y
i
Cr
i
Y
i+1
Cb
i
Table 25: RGB Ordering in Default Mode
Mode (Swap Disabled) Byte D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
RGB 565 Odd R
7
R
6
R
5
R
4
R
3
G
7
G
6
G
5
Even G
4
G
3
G
2
B
7
B
6
B
5
B
4
B
3
RGB 555 Odd 0 R
7
R
6
R
5
R
4
R
3
G
7
G
6
Even G
4
G
3
G
2
B
7
B
6
B
5
B
4
B
3
RGB 444x Odd R
7
R
6
R
5
R
4
G
7
G
6
G
5
G
4
Even B
7
B
6
B
5
B
4
0 0 0 0
RGB x444 Odd 0 0 0 0 R
7
R6
6
R
5
R
4
Even G
7
G
6
G
5
G
4
B
7
B
6
B
5
B
4
PIXCLK
Data[7:0]
Frame Valid/
Line Valid
XXXXXX XXX XXX XXXXXX
Note: Frame_Valid leads Line_Valid by 6 PIXCLKs.
Note: Frame_Valid trails
Line_Valid by 6 PIXCLKs.
t
PFL
t
PLL
t
PD
t
PD
t
PFH
t
PLH
Pxl_0 Pxl_1 Pxl_2 Pxl_n