Datasheet
Table Of Contents
- 1/3.2-Inch System-On-A-Chip (SOC) CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- General Description
- Feature Overview
- Typical Connection
- Ballout and Interface
- Architecture Overview
- Registers and Variables
- Registers
- Registers
- IFP Registers, Page 1
- IFP Registers, Page 2
- JPEG Indirect Registers
- Table 8: JPEG Indirect Registers (See Registers 30 and 31, Page 2)
- Firmware Driver Variables
- Table 9: Drivers IDs
- Table 10: Driver Variables-Monitor Driver (ID = 0)
- Table 11: Driver Variables-Sequencer Driver (ID = 1)
- Table 12: Driver Variables-Auto Exposure Driver (ID = 2)
- Table 13: Driver Variables-Auto White Balance (ID = 3)
- Table 14: Driver Variables-Flicker Detection Driver (ID = 4)
- Table 15: Driver Variables-Auto Focus Driver (ID = 5)
- Table 16: Driver Variables-Auto Focus Mechanics Driver (ID = 6)
- Table 17: Driver Variables-Mode/Context Driver (ID = 7)
- Table 18: Driver Variables-JPEG Driver (ID = 9)
- Table 19: Driver Variables-Histogram Driver (ID = 11)
- MCU Register List and Memory Map
- JPEG Indirect Registers
- Output Format and Timing
- Sensor Core
- Feature Description
- PLL Generated Master Clock
- PLL Setup
- Window Control
- Pixel Border
- Readout Modes
- Figure 20: 6 Pixels in Normal and Column Mirror Readout Modes
- Figure 21: 6 Rows in Normal and Row Mirror Readout Modes
- Table 30: Skip Values
- Figure 22: 8 Pixels in Normal and Column Skip 2x Readout Modes
- Figure 23: 16 Pixels in Normal and Column Skip 4x Readout Modes
- Figure 24: 32 Pixels in Normal and Column Skip 8x Readout Modes
- Figure 25: 64 Pixels in Normal and Column Skip 16x Readout Modes
- Table 31: Row Addressing
- Table 32: Column Addressing
- Frame Rate Control
- Context Switching
- Integration Time
- Flash STROBE
- Global Reset
- Analog Signal Path
- Analog Inputs AIN1-AIN3
- Firmware
- Firmware
- Start-Up and Usage
- General Purpose I/O
- Introduction
- GPIO Output Control Overview
- Waveform Programming
- Notification Signals
- Digital and Analog Inputs
- GPIO Software Drivers
- Auto Focus
- Figure 42: Search for Best Focus
- Figure 43: Scene with Two Potential Focus Targets at Different Distances from Camera
- Figure 44: Dependence of Luminance-Normalized Local Sharpness Scores on Lens Position
- Figure 45: Example of Position Weight Histogram Created by AF Driver
- Figure 46: Auto Focus Windows
- Figure 47: Computation of Sharpness Scores and Luminance Average for an AF Window
- Table 41: Examples of AF Filters that can be Programmed into the MT9D111
- Spectral Characteristics
- Electrical Specifications
- Packaging
- Appendix A: Two-Wire Serial Register Interface
- Protocol
- Sequence
- Bus Idle State
- Start Bit
- Stop Bit
- Slave Address
- Data Bit Transfer
- Acknowledge Bit
- No-Acknowledge Bit
- Page Register
- Sample Write and Read Sequences
- Figure 52: WRITE Timing to R0x09:0-Value 0x0284
- Figure 53: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 54: WRITE Timing to R0x09:0-Value 0x0284
- Figure 55: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 56: Two-Wire Serial Bus Timing Parameters
- Table 46: Two-wire Serial Bus Characteristics
- Revision History
PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__5_REV5.fm - Rev. B 2/06 EN
101 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
JPEG Indirect Registers
Micron Confidential and Proprietary
LineCnt 0x1046/7
Line counter (read-only)
Current line number incremented at every line end:
—0 at frame start
—0x07FF at frame end
Address 0x1046 (MSB) must be read first.
ClockCnt 0x1048-B
Clock counter (read-only)
Address 0x1048 (MSB) must be read first.
RestartCode 0x104C
Warm restart register
Bits 2:0
—Warm restart code
Value of 7 indicates watchdog caused reset.
InfoCode 0x104D
Debug information, maps to two-wire serial interface R195[15:8].
Watchdog 0x104E
Watchdog register
Bit 3
—1 watchdog causes XIRQ, 0=reset
Bits 2:0
—0 disable, other-frame number that triggers watchdog (1 = next
frame)
Clear Sleep reg. to reset watchdog.
BootMode 0x104F
Boot mode, read-only. Maps to two-wire serial interface R195[7:0].
Register I/O Bus Master
WRITE_IOPAGE 0x1060
Register page number to write
[0]
—page number (IFP/Sensor core)
WRITE_IOADR 0x1061
Register address to write
IODATA 0x1062/3
Data from read transaction (read)
Data for write operation (write)
Write data to this register to initiate a register bus write transaction.
READ_IOPAGE 0x1064
Register page number to read
Bit[0] page number (IFP/Sensor core)
READ_IOADR 0x1065
Register address for read transaction
Write to initiate read transaction
IOSTATUS 0x1066
I/O bus transaction status (read-only)
[7]
—1 = write busy
[6]—1 = read busy
Read 0 to ensure I/O transaction is complete.
VARIABLE ACCESS (SLAVE DMA)
R200 0x1050/1
Driver table pointer
Table 21: Special Function Register List (continued)
Name Hex# Description