Datasheet
Table Of Contents
- 1/3.2-Inch System-On-A-Chip (SOC) CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- General Description
- Feature Overview
- Typical Connection
- Ballout and Interface
- Architecture Overview
- Registers and Variables
- Registers
- Registers
- IFP Registers, Page 1
- IFP Registers, Page 2
- JPEG Indirect Registers
- Table 8: JPEG Indirect Registers (See Registers 30 and 31, Page 2)
- Firmware Driver Variables
- Table 9: Drivers IDs
- Table 10: Driver Variables-Monitor Driver (ID = 0)
- Table 11: Driver Variables-Sequencer Driver (ID = 1)
- Table 12: Driver Variables-Auto Exposure Driver (ID = 2)
- Table 13: Driver Variables-Auto White Balance (ID = 3)
- Table 14: Driver Variables-Flicker Detection Driver (ID = 4)
- Table 15: Driver Variables-Auto Focus Driver (ID = 5)
- Table 16: Driver Variables-Auto Focus Mechanics Driver (ID = 6)
- Table 17: Driver Variables-Mode/Context Driver (ID = 7)
- Table 18: Driver Variables-JPEG Driver (ID = 9)
- Table 19: Driver Variables-Histogram Driver (ID = 11)
- MCU Register List and Memory Map
- JPEG Indirect Registers
- Output Format and Timing
- Sensor Core
- Feature Description
- PLL Generated Master Clock
- PLL Setup
- Window Control
- Pixel Border
- Readout Modes
- Figure 20: 6 Pixels in Normal and Column Mirror Readout Modes
- Figure 21: 6 Rows in Normal and Row Mirror Readout Modes
- Table 30: Skip Values
- Figure 22: 8 Pixels in Normal and Column Skip 2x Readout Modes
- Figure 23: 16 Pixels in Normal and Column Skip 4x Readout Modes
- Figure 24: 32 Pixels in Normal and Column Skip 8x Readout Modes
- Figure 25: 64 Pixels in Normal and Column Skip 16x Readout Modes
- Table 31: Row Addressing
- Table 32: Column Addressing
- Frame Rate Control
- Context Switching
- Integration Time
- Flash STROBE
- Global Reset
- Analog Signal Path
- Analog Inputs AIN1-AIN3
- Firmware
- Firmware
- Start-Up and Usage
- General Purpose I/O
- Introduction
- GPIO Output Control Overview
- Waveform Programming
- Notification Signals
- Digital and Analog Inputs
- GPIO Software Drivers
- Auto Focus
- Figure 42: Search for Best Focus
- Figure 43: Scene with Two Potential Focus Targets at Different Distances from Camera
- Figure 44: Dependence of Luminance-Normalized Local Sharpness Scores on Lens Position
- Figure 45: Example of Position Weight Histogram Created by AF Driver
- Figure 46: Auto Focus Windows
- Figure 47: Computation of Sharpness Scores and Luminance Average for an AF Window
- Table 41: Examples of AF Filters that can be Programmed into the MT9D111
- Spectral Characteristics
- Electrical Specifications
- Packaging
- Appendix A: Two-Wire Serial Register Interface
- Protocol
- Sequence
- Bus Idle State
- Start Bit
- Stop Bit
- Slave Address
- Data Bit Transfer
- Acknowledge Bit
- No-Acknowledge Bit
- Page Register
- Sample Write and Read Sequences
- Figure 52: WRITE Timing to R0x09:0-Value 0x0284
- Figure 53: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 54: WRITE Timing to R0x09:0-Value 0x0284
- Figure 55: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 56: Two-Wire Serial Bus Timing Parameters
- Table 46: Two-wire Serial Bus Characteristics
- Revision History
PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__5_REV5.fm - Rev. B 2/06 EN
100 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
JPEG Indirect Registers
Micron Confidential and Proprietary
Special Function Registers - System
Table 21: Special Function Register List
Name Hex# Description
Native Registers
PACTL 0x1026
Pulse accumulator control
[2]
—IC4/OC5 Input capture 4/output compare 5 select
OPTION 0x1039
System configuration options register
[5]
— IRQE 0 = low level sensitive,1 = falling edge sensitive
HPRIO 0x103C
Highest priority I-Bit interrupt and miscellaneous register
[5]
—MDA mode select A bit
[3:0]—PSEL[3:0] priority select bits
INIT 0x103D
RAM and I/O mapping register
[3:0]
—REG[3:0] RAM map position bits
[7:4]
—RAM[3:0] register block position bits
Math Coprocessor Registers
CREG[31:0] 0x10C0–0x10C3
32-bit data register
ALUC 0x10C4
Arithmetic logic unit control register
[7]
—signed number enable
[6]
—division enable
[5]—multiply with accumulated product enable
[4]—division compensation for concatenated quotient enable
[3]
—function start trigger bit
[2]—overflow interrupt enable
[1]—divide by zero interrupt enable
[0]
—arithmetic operation completion interrupt enable
AREG[15:0] 0x10C5–0x10C6
16-bit data register
BREG 0x10C70–0x10C8
16-bit data register
ALUF 0x10C9
Arithmetic logic unit flag register
[7]
—negative result flag
[6]—remainder zero flag
[5:3]
—always “0”
[2]—overflow MSB on CREG detected flag
[1]—divide by zero detected flag; cleared by writing a “1”
[0]
—arithmetic operation completed flag; cleared by writing a “1”
SLEEP REGISTERS
Sleep 0x1040
Sleep register
1
—“1” = GPIO wakeup
0
—“1” = line counter wakeup; write “1” to clear
Read this register to attempt sleeping
WakeupLineCnt 0x1042/3
Line Counter Wakeup (MSB)
15
—“0” = wake up on positive edge/level
14
—“1” = wake up on level, “0”= on edge
[10:0]—Line number
The following values are special:
0x07FF
—disable wakeup
0x07FE
—wake up on SOC frame enable
0x07FD
—wake up on sensor frame enable
0x07FC
—wake up on JPEG frame enable
0x07FB
—wake up on FIFO frame enable