Data Sheet
CMOS VGA (640 x 480) image sensor with OmniPixel3-HS™ technology
OV7675/OV7175
proprietary to OmniVision Technologies PRODUCT SPECIFICATION version 2.0
0x20~
0x23
NOT USED – – Not Used
0x24 AEW 0x62 RW
AGC/AEC - Stable Operating Region
(Upper Limit)
0x25 AEB 0x58 RW
AGC/AEC - Stable Operating Region
(Lower Limit)
0x26 VPT 0x93 RW
AGC/AEC Fast Mode Operating Region
Bit[7:4]: High nibble of upper limit of fast mode
control zone
Bit[3:0]: High nibble of lower limit of fast mode
control zone
0x27~
0x29
NOT USED – – Not Used
0x2A EXHCH 0x00 RW
Dummy Pixel Insert
Bit[7:4]: Dummy pixel insert in horizontal
direction[11:8] (2 MSBs in REGCA[7:6]
(0xCA), 8 LSBs in EXHCL (0x2B))
Bit[3:2]: HSYNC falling edge delay 2 MSBs (see
HSYEN[7:0] (0x31) for 8 LSBs)
Bit[1:0]: HSYNC rising edge delay 2 MSBs (see
HSYST[7:0] (0x30) for 8 LSBs)
0x2B EXHCL 0x00 RW
Bit[7:0]: Dummy pixel insert in horizontal
direction[7:0]
(see REGCA[7:6] (0xCA) and
EXHCH[7:4] (0x2A))
0x2C NOT USED – – Not Used
0x2D ADVFL 0x00 RW
LSBs of Insert Dummy Lines in Vertical Direction
(1 bit equals 1 line)
0x2E ADVFH 0x00 RW MSBs of Insert Dummy Lines in Vertical Direction
0x2F YAVE 0x00 RW Y/G Channel Average Value
0x30 HSYST 0x08 RW
HSYNC Rising Edge Delay 8 LSBs
(see EXHCH[1:0] (0x2A) for 2 MSBs)
0x31 HSYEN 0x30 RW
HSYNC Falling Edge Delay
(see EXHCH[3:2] (0x2A) for 8 MSBs)
0x32 HREF 0x80 RW
HREF Control
Bit[7:6]: HREF edge offset to data output
Bit[5:3]: HREF end 3 LSBs (8 MSBs at
HSTOP (0x18))
Bit[2:0]: HREF start 3 LSBs (8 MSBs at HSTART
(0x17))
table 7-1 system control registers (sheet 6 of 17)
address
register name
default
value
R/W
description
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