Data Sheet

10.13.2009 PRODUCT SPECIFICATION proprietary to OmniVision Technologies
7-5
0x15 COM10 0x00 RW
Common Control 10
Bit[7]: Debug mode
Bit[6]: HREF changes to HSYNC
Bit[5]: PCLK output option
0: Free running PCLK
1: PCLK does not toggle during
horizontal blank
Bit[4]: PCLK reverse
Bit[3]: HREF reverse
Bit[2]: VSYNC option
0: VSYNC changes on falling edge of
PCLK
1: VSYNC changes on rising edge of
PCLK
Bit[1]: VSYNC negative
Bit[0]: HSYNC negative
0x16 NOT USED – – Not Used
0x17 HSTART 0x11 RW
Output Format - Horizontal Frame (HREF column)
start 8 MSBs (3 LSBs are at HREF[2:0] (0x32))
0x18 HSTOP 0x61 RW
Output Format - Horizontal Frame (HREF column)
end 8 MSBs (3 LSBs are at HREF[5:3] (0x32))
0x19 VSTART 0x03 RW
Output Format - Vertical Frame (row) start 8 MSBs (2
LSBs are at VREF[1:0] (0x03))
0x1A VSTOP 0x7B RW
Output Format - Vertical Frame (row) end 8 MSBs (2
LSBs are at VREF[3:2] (0x03))
0x1B PSHFT 0x00 RW
Data Format - Pixel Delay Select (delays timing of the
D[7:0] data relative to HREF in pixel units)
Range: [00] (no delay) to [FF] (256 pixel delay which
accounts for whole array)
0x1C MIDH 0x7F R Manufacturer ID High Byte
0x1D MIDL 0xA2 R Manufacturer ID Low Byte
0x1E MVFP 0x01 RW
Mirror/VFlip Enable
Bit[7:6]: Debug mode
Bit[5]: Mirror
0: Normal image
1: Mirror image
Bit[4]: VFlip enable
0: Normal image
1: Vertically flip image
Bit[3:0]: Debug mode
0x1F DEBUG MODE – – Debug Mode
table 7-1 system control registers (sheet 5 of 17)
address register name
default
value R/W description
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