Data Sheet

CMOS VGA (640 x 480) image sensor with OmniPixel3-HS™ technology
OV7675/OV7175
proprietary to OmniVision Technologies PRODUCT SPECIFICATION version 2.0
2.3 power management
The OV7675/OV7175 requires 2.8V (typical) for analog and 1.8V or 2.8V (typical) for I/O. The internal regulator provides
1.5V for core logic with I/O power (DOVDD).
The OV7675/OV7175 includes built-in power management circuitry to optimize battery life. Only system related functions
are always powered on. Sensor and ISP functions are powered off in power down mode. Also, during the power on
sequence of the whole device, these functions are powered on after system functions are powered on.
During power down, values of all the registers are maintained and are restored after the sensor power is resumed. In
power down mode, the clock input from the system can be turned OFF inside the sensor even if the external clock source
is still clocking.
2.4 power ON reset generation
The OV7675/OV7175 includes an on-chip initial power-on reset feature, which will automatically detect core power at
stable state and reset the image sensor.
2.5 DOVDD power requirements
The OV7675/OV7175 requires two power supplies, AVDD and DOVDD. For different DOVDD registers 0xB8[6:3] must
be set to the settings in table 2-2.
2.6 system clock control
The OV7675/OV7175 has on-chip PLL which generates the system clock with 6~27 MHz input clock. A programmable
clock divider is needed to generate a different frequency for the system. For input clock lower than 6 MHz (1.5 <
XVCLK
<6), PLL should be bypassed.
table 2-2 DOVDD power requirements
DOVDD 0xB8[6:3]
1.8 V 4’h1
2.8 V 4’h2
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