User guide

Arch Meter Corporation PS1000 Ver1.2
PS1000Rev. 1.2 May 2006
5/ 67
www.archmeter.com
XTLO O System Crystal output
SCLK I/O SPI Clock input/output signal. The I/O selection depends on the SPI is
in master or slave mode. In the master mode, the maximum clock rate is
SYSCLK/4
SPICS O SPI CS control signal, active low
SO O SPI SO output
SI I SPI SI input
FSX I/O SSP transmit frame sync signal
DX I/O SSP transmit data signal
CLK O SSP CLK, the transmit and received clock. The maximum clock rate is
SYSCLK/4
DR O SSP receive data signal
FSR O SSP receive frame sync signal
SCL I/O I2C clock
SDA I/O I2C Address/Data
VCM1 O Current Phase A/B ADC reference output(VCC3A/2)
IBM I Phase B Current input(-)
IBP I Phase B Current input(+)
IAP I Phase A Current input(+)
IAM I Phase A Current input(-)
VAM I Voltage input(-)
VAP I Voltage input(+)
VCM2 O Voltage ADC reference output(VCC3A/2)
VLCD O LCD bias power supply output
V1 I LCD bias input 1
V2 I LCD bias input 2
V3 I LCD bias input 3
COM3~0 O LCD COM output (maximum driving current 200uA)
SEG0~39 O LCD Segment output (maximum driving current 20uA)
RST I Chip Reset, active high
EA I 8051 MCU EA control signal
1: Internal ROM
0: External ROM
PSEN I/O 8051 PSEN control pin
ALE I/O 8051 ALE control signal
MODE2-0 I Operation Mode selection
000 Normal Operation (1)
001 ICP Mode
010 External 51 Mode (1)
011 Normal Operation (2)
100 Memory Test Mode
101 External 51 Mode (2)
110 Analog Test Mode (Reserved)
111 Memory BIST Mode (Reserved)
P0.0 I/O 8051 P0 I/O port bit 0 (mapped to the AD0)
P0.1 I/O 8051 P0 I/O port bit 1 (mapped to the AD1)
P0.2 I/O 8051 P0 I/O port bit 2 (mapped to the AD2)
P0.3 I/O 8051 P0 I/O port bit 3 (mapped to the AD3)
P0.4 I/O 8051 P0 I/O port bit 4 (mapped to the AD4)
P0.5 I/O 8051 P0 I/O port bit 5 (mapped to the AD5)