User guide

Arch Meter Corporation PS1000 Ver1.2
PS1000Rev. 1.2 May 2006
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www.archmeter.com
11. RTC
The PS1000 has one RTC (Real-Time Clock) circuit. It can keep one clock count
reference base one 32.768 KHz crystal.
This RTC circuit can make a different configuration base on the RTCCFG register.
RTCCFG (0xFE28)
B7 B6 B5 B4 B3 B2 B1 B0
1
UPD
RTCADJ[5:0]
UPD: RTC update
1: Update
0: no update (Default)
RTCADJ[5:0]: RTC Frequency Adjust (Hz), 2’s complement
…
000010: RTCCLK = 32768 + 2Hz
000001: RTCCLK = 32768 + 1Hz
000000: RTCCLK = 32768Hz
111111: RTCCLK = 32768 - 1Hz
111110: RTCCLK = 32768 - 2Hz
…
The RTC circuit has one clock divider which can adjust the RTC clock rate
used for RTC clock bias tuning. This divider must control very carefully to prevent
the RTC clock error.
RTCCFG2(0xFE3C)
B7 B6 B5 B4 B3 B2 B1 B0
RTCTM[2:0] x RTCFADJ[3:0]
This register is used for configure the RTC test mode and fine adjust the RTC
frequency.
RTCTM[2:0] RTC Test Mode control
Must always set as 000