User guide

Arch Meter Corporation PS1000 Ver1.2
PS1000Rev. 1.2 May 2006
50/ 67
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CKEN CLKDIV
CLKEN: Enable SSP clock divider
0: Disable, default MCUCLK/4 (same as N = 0)
1: Enable, MCUCLK/n
CLKDIV: SSP clock source divider
N: SSPCLK = MCUCLK / (2*(N+1))
SSPDXRL (SFR 0xAC)
B7 B6 B5 B4 B3 B2 B1 B0
D7 D6 D5 D4 D3 D2 D1 D0
SSPDXRH (SFR 0xAB)
B7 B6 B5 B4 B3 B2 B1 B0
D15 D14 D13 D12 D11 D10 D9 D8
SSPRXRL (SFR 0xAE)
B7 B6 B5 B4 B3 B2 B1 B0
D7 D6 D5 D4 D3 D2 D1 D0
SSPRXRH (SFR 0xAD)
B7 B6 B5 B4 B3 B2 B1 B0
D15 D14 D13 D12 D11 D10 D9 D8
SSPSTA (SFR 0xAF)
B7 B6 B5 B4 B3 B2 B1 B0
XINT XRDY XEMP XLoad RINT RRDY RSRFULL Read
XINT: Transmitter interrupt, only for few cycle
XRDY: ‘1’ indicate the transmitter is ready for transmit.
XEMP: Transmit buffer is empty; it can load the new data to
transmitter.
XLoad
RINT: Receiver interrupt, only for little cycle.
RRDY: ‘1’ indicate the received data from SSP bus. The DRR register
must be read immediately.
RSRFULL: 1’ indicate the receiver buffer overrun.
Read: Set as ‘1’ to indicate the DRR already read, this bit will auto
clear when the RRDY will return to ‘0’
The SSP interface can control by DSP or MCU. It can select by the DSPCFG
register (Bit5). When the SSP is controlled by the DSP, it only can be the TX mode.
It will output the 3 channel ADC data and 2 current gain information.