User guide

Arch Meter Corporation PS1000 Ver1.2
PS1000Rev. 1.2 May 2006
49/ 67
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10. SSP
The PS1000 has one SSP interface. This interface is compatible with TI serial
peripheral interface specification.
This SSP interface is controlled by the SSPCFG / SSPCKL / SSPDXR /
SSPRXR / SSPSTA registers. These registers are mapped at the SFR memory
space. The setting for these register are
SSPCFG1 (SFR 0xBB)
B7 B6 B5 B4 B3 B2 B1 B0
N/A TXEN RXEN TXM MCM FSM FO DLB
TXEN: SSP TX I/F Enable
0: SSP TX I/F Disable (Default)
1: SSP TX I/F Enable
RXEN: B5 SSP RX I/F Enable
0: SSP RX I/F Disable (Default)
1: SSP RX I/F Enable
TXM : Frame Sync Mode (TXM)
0: FSX is External sync
1: FSX is internal sync
MCM: CLK Mode (MCM)
0: CLKX comes from External Clock (default)
1: CLKX comes from Internal Clock
FSM: Frame Sync Mode (FSM)
0: Continuous mode (default)
1: Burst Mode
FO: Data Length Control (FO)
0: 16 bits
1: 8 bits
DLB: Digital loop-back Control
0: Disable
1: Enable
SSPCFG2 (SFR 0xBC)
B7 B6 B5 B4 B3 B2 B1 B0