User guide

Arch Meter Corporation PS1000 Ver1.2
PS1000Rev. 1.2 May 2006
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www.archmeter.com
I2CDATR register contains the data to be transmitted or the data received.
The micro controller can read and write to this 8-bit register while it is not in the
process of shifting a byte. Thus this register should only be accessed when the SI
bit is set. Data in I2CDATR remains stable as long as the SI bit is set. Data in
I2CDATR is always shifted from right to left: the first bit to be transmitted is the
MSB(bit 7), and after a byte has been received, the first bit of received data is
located at the MSB of I2CDATR.
9.2 Operation Modes
The I
2
C device provides four operation modes: Master Transmitter Mode,
Master Receiver Mode, Slave Transmitter Mode and Slave Receiver Mode.
9.2.1 Master Transmitter Mode
In this mode data is transmitted from master to slave. Before the master transmitter
mode can be entered, I2CCTLR must be initialized as follows:
7 6 5 4 3 2 1 0
I2CEN STA STO SI AA - - -
I
2
CCTLR
1 0 0 0 0 - - -
I2CEN must be set to 1 to enable the I
2
C function. If the AA bit is 0, it will not
acknowledge its own slave address or the general call address in the event of
another device becoming master of the bus and it can not enter slave mode. STA,
STO and SI bits must be cleared to 0.
The first byte transmitted contains the slave address of the receiving device
(7 bits) and the data direction bit. In this case, the data direction bit (R/W) will be
logic 0 indicating a write. Data is transmitted 8 bits at a time. After each byte is
transmitted, an acknowledge bit is received. START and STOP conditions are
output to indicate the beginning and the end of a serial transfer.
The I
2
C will enter Master Transmitter Mode by setting the STA bit. The I
2
C
logic will send the START condition as soon as the bus is free. After the START