User guide

Arch Meter Corporation PS1000 Ver1.2
PS1000Rev. 1.2 May 2006
37/ 67
www.archmeter.com
I2CCTLR7 I
2
CEN I2C enable bit
1 = enables the I2C interface
0 = disables the I2C interface
I2CCTLR6 STA Start flag
1 = I
2
C enters master mode and generates a START
condition. When the I
2
C interface is already in
master mode and some data has been transmitted or
received, it transmits a repeated START condition.
0 = no START condition or repeated START
condition will be generated
I2CCTLR5 STO STOP flag
1 = in master mode, a STOP condition is transmitted
to the I
2
C bus. When the bus detects the STOP
condition, it will clear STO bit automatically.
In slave mode, setting this bit can recover from an
error condition. In this case, no STOP condition is
transmitted to the bus. The hardware behaves as if a
STOP condition has been received and it switches to
“not addressed” Slave Receiver Mode. The STO flag
is cleared by hardware automatically
I2CCTLR4 SI I
2
C interrupt flag
1 = one of the 25 possible I
2
C states is entered, an
interrupt is requested, it is cleared automatically
when the I
2
C status register is cleared
I2CCTLR3 AA Assert acknowledge flag
1 = an acknowledge (low level to SDA) will be
returned during the acknowledge clock pulse on the
SCL line on the following situations:
(1) The “own slave address” has been received.
(2)
The general call address has been received while
the general call bit (GC) in I2ADR is set.
(3) A data byte has been received while the I
2
C
interface is in the Master Receiver Mode.
(4) A data byte has been received while the I
2
C
interface is in the addressed Slave Receiver
Mode.
0 = an not acknowledge (high level to SDA) will be
returned during the acknowledge clock pulse on the
SCL line on the following situations:
(1) A data byte has been received while the I
2
C
interface is in the Master Receiver Mode.
(2) A data byte has been received while the I
2
C
interface is in the Slave receiver Mode
I2CCTLR2-0 - Reserved for future use