User guide

Arch Meter Corporation PS1000 Ver1.2
PS1000Rev. 1.2 May 2006
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0 – 400 KHz. Thus the values of I2CCKHR and I2CCKLR have some restrictions.
Some relationship between the system clock, bit data rate, and values of registers
are shown in table 1-1. Note that the values for both registers greater than three
system clocks are recommended.
I
2
C clock rates selection
Bit data rate (Kbit/sec) at f
SYS_CLK
I
2
CCKHR + I
2
CCKLR
5 MHz 25MHz
13 384 -
14 357
20 250
50 100
70 71 357
100 50 250
200 25 75
500 10 50
I2CCTLR (I
2
C Control Register)
I2CCTLR(SFR 0xB4) Reset value 00h
B7 B6 B5 B4 B3 B2 B1 B0
I2CEN STA STO INTR AA - - -
This register can be written or read. There are two bits affected by hardware:
the INTR bit and STO bit. The INTR bit is set by hardware and the STO bit is
cleared by hardware.
The STA bit is START flag. Setting this bit causes the I
2
C interface to enter
master mode and attempt transmitting a START condition or transmitting a
repeated START condition when it is already in master mode.
The STO bit is STOP flag. Setting this bit causes the I
2
C interface to transmit
a STOP condition in master mode, or recovering from an error condition in slave
mode.
If the STA and STO are both set, then a STOP condition is transmitted to the
I
2
C-bus if it is in master mode, and transmits a START condition afterwards. If it is
in slave mode, an internal STOP condition will be generated, but it is not
transmitted to the bus.
BIT SYMBOL FUNCTION