User guide
Arch Meter Corporation PS1000 Ver1.2
PS1000Rev. 1.2 May 2006
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www.archmeter.com
9. I
2
C
The PS1000 has one I
2
C interface. This I
2
C interface is controlled by the
I2CCKH/I2CCKL/I2CCTL/I2CSTA/I2CDAT registers. These registers are
mapped at the SFR memory space. The setting for these registers are
The I
2
C-bus uses two wires, serial clock (SCL) and serial data (SDA) to
transfer information between devices connected to the bus, and has the following
features:
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption
of serial data on the bus
Serial clock synchronization allows devices with different bit rates to
communicate via one serial bus
Serial clock synchronization can be used as a handshake mechanism to
suspend and resume serial transfer
The I
2
C-bus may be used for test and diagnostic purposes
A typical I
2
C-bus configuration is shown in below. Depending on the state of the
direction bit (R/W), two types of data transfers are possible on the I
2
C-bus:
Data transfer from a master transmitter to a slave receiver. The first byte
transmitted by the master is the slave address. Next follows a number of data
bytes. The slave returns an acknowledge bit after each received byte.
Data transfer from a slave transmitter to a master receiver. The first byte (the
slave address) is transmitted by the master. The slave then returns an
acknowledge bit. Next follows the data bytes transmitted by the slave to the
master. The master returns an acknowledge bit after all received bytes other
than the last byte. At the end of the last received byte, a “not acknowledge” is
returned. The master device generates all of the serial clock pulses and the
START and STOP conditions. A transfer is ended with a STOP condition or
with a repeated START condition. Since a repeated START condition is also
the beginning of the next serial transfer, the I
2
C-bus will not be released.
I
2
C-bus configuration