User guide

Arch Meter Corporation PS1000 Ver1.2
PS1000Rev. 1.2 May 2006
30/ 67
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8. SPI
The PS1000 has one SPI interface which can be master or slave.
This SPI interface is controlled by the SPICTL/SPIDAT/SPISTA register. These
registers are mapped at the SFR memory space. The setting for these register are
SPICTL(SFR 0xBD)
B7 B6 B5 B4 B3 B2 B1 B0
EN SS MST CPOL CPHA Baud Rate Selection
EN SPI enable bit
1: enable the SPI interface
0: disable the SPI interface
SS SS disable bit
1: disable SS in both master and slave modes, no MODF interrupt
request is generated.
0: enable SS in both master and slave modes
MST Serial peripheral master mode
1: configure the SPI as a master
0: configure the SPI as a slave
CPOL Clock polarity
1: SCK set to “1” in idle state
0: SCK set to “0” in idle state
CPHA Clock phase
1: have the data sampled when the SCK returns to idle state
0: have the data sampled when the SCK leaves the idle state
Baud Rate SPI clock selection
000 MCUCLK / 1
001 MCUCLK / 2
010 MCUCLK / 4
011 MCUCLK / 8
100 MCUCLK / 16
101 MCUCLK / 32
110 MCUCLK / 64
111 MCUCLK / 128
SPIDAT
SPIDAT(SFR 0xBF)
B7 B6 B5 B4 B3 B2 B1 B0
D7 D6 D5 D4 D3 D2 D1 D0
SPISTA