User guide

Arch Meter Corporation PS1000 Ver1.2
PS1000Rev. 1.2 May 2006
11/ 67
www.archmeter.com
10011 SYSCLK / 40
46.2
42.3
10100 SYSCLK / 42
44.0
40.3
10101 SYSCLK / 44
42.0
38.5
10110 SYSCLK / 46
40.1
36.8
10111 SYSCLK / 48 38.
5
35.3
11000 SYSCLK / 50
36.9
33.8
11001 SYSCLK / 52
35.5
32.5
11010 SYSCLK / 54
34.2
31.3
11011 SYSCLK / 56
33.0
30.2
11100 SYSCLK / 58
31.8
29.2
11101 SYSCLK / 60
30.8
28.2
11110 SYSCLK / 62
29.8
27.3
11111 SYSCLK / 64
28.8
26.4
3.3 DSP Clock Setting
The PS1000 can set the different DSP operation clock during the different
operation condition. It also can help to save the power.
DSPCFG (0xFE25)
B7 B6 B5 B4 B3 B2 B1 B0
EN RDY READ SSPM DSPDIV
EN: DSP Enable or Disable
1: Enable DSP
0: Disable DSP
RDY: DSP ready flag
1: DSP data is ready; it must read by the MCU
0: DSP data is not ready or already read by MCU
READ: MCU Read data flag
MCU set this flag to clear the RDY flag, the “0” is clear. So, when DSP
is operating the READ must set as ‘1’. When the MCU check the RDY
is set to ‘1’, MCU must toggle READ flag (1-0-1) to clear the RDY flag.
SSPM: Specific the SSP interface is controlled by DSP or MCU.
1: SSP I/F is controlled by DSP
0: SSP I/F is controlled by MCU
DSPDIV: DSP clock Divider
DSPDIV[3:0] DSPCLK 22MHz 24MHz