User guide

Arch Meter Corporation PS1000 Ver1.2
PS1000Rev. 1.2 May 2006
9/ 67
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0100 SCLK / 5 4.40 4.80
0101 SCLK / 6 3.67 4.00
0110 SCLK / 7 3.14 3.43
0111 SCLK / 8 2.75 3.00
1000 SCLK / 9 2.44 2.67
1001 SCLK / 10 2.20 2.40
1010 SCLK / 11 2.00 2.18
1011 SCLK / 12 1.83 2.00
1100 SCLK / 13 1.69 1.85
1101 SCLK / 14 1.57 1.71
1110 SCLK / 15 1.47 1.60
1111 SCLK / 16 1.38 1.50
3.2 ADC Clock Setting
The IA/IB/VA input ADC clock will be set as 1/2 system clock. For the ADC
sampling rate, The PS1000 can set the different ADC sampling rate for different
application. This setting is controlled by the ADCCFG register. The ADCCFG
configuration is
ADCCFG (0xFE21)
B7 B6 B5 B4 B3 B2 B1 B0
EN ADCMODE Half-Rate ADCDIV
ADC mode: ADC format selection
0x: Unsigned
10: Signed 2’s complement
11: Signed 1’s complement
Half-Rate
0: Normal ADC data rate
1: Half ADC data rate
ADCDIV: ADC sampling rate selection
SYSCLK(24M) SYSCLK(22M)
0000 ADC_CLK / 375 32.00K 29.33K
0001 ADC_CLK / 750 16.00K 14.67K
0010 ADC_CLK / 768 15.63K 14.32K
0011 ADC_CLK / 1536 7.81K 7.16K
0100 ADC_CLK / 1500 8.00K 7.33K
0101 ADC_CLK / 500 24.00K 22.00K
0110 ADC_CLK / 250 48.00K 44.00K