Arch Meter Corporation Rm.807, Bldg.53,195 Sec. 4 Chung Hsing Rd., Chutung, Hsinchu, Taiwan 310, R.O.C. Tel: 886-3-591-0234 Fax: 886-3-591-0342 E-mail : sales@archmeter.com.tw http:// www.archmeter.com PS1000 User Guide V1.
Arch Meter Corporation PS1000 Ver1.2 Index Index ..............................................................................................................................1 1. System Architecture ...................................................................................................3 2. Mode Control .............................................................................................................7 3. Clock Setting.................................................................
Arch Meter Corporation PS1000Rev. 1.2 May 2006 PS1000 2/ 67 Ver1.2 www.archmeter.
Arch Meter Corporation PS1000 Ver1.2 1. System Architecture The PS1000 is an ASIC for the 1P3W (One-Phase, Three-Wire) Power Meter (Energy Meter) application. The PS1000 integrated all the function needs for energy meter application. The system architecture is shown in figure 1. LCD Display Vref IA AGC ADC IB AGC ADC Temp.
Arch Meter Corporation PS1000 Ver1.
Arch Meter Corporation PS1000 Ver1.2 XTLO O System Crystal output SCLK I/O SPICS SO SI O O I SPI Clock input/output signal. The I/O selection depends on the SPI is in master or slave mode. In the master mode, the maximum clock rate is SYSCLK/4 SPI CS control signal, active low SPI SO output SPI SI input FSX DX CLK I/O I/O O DR FSR O O SSP transmit frame sync signal SSP transmit data signal SSP CLK, the transmit and received clock.
Arch Meter Corporation P0.6 P0.7 P1.0(optional) P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4(optional) P3.5(optional) P3.6 P3.7 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PS1000Rev. 1.2 May 2006 PS1000 Ver1.
Arch Meter Corporation PS1000 Ver1.2 2. Mode Control The PS1000 has several modes for different operation. The mode is controlled by the MODE and EA setting. Here is the configuration list.
Arch Meter Corporation PS1000 Ver1.2 3. Clock Setting The operation frequency of some PS1000 internal function blocks, like the ADC, MCU, DSP and LCD can be adjusted depends on operation condition. It can be configured with some internal register. The next section will describe how to program these registers. When change these registers setting, please make sure that is matched with the system requirement. 3.
Arch Meter Corporation 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PS1000 SCLK / 5 SCLK / 6 SCLK / 7 SCLK / 8 SCLK / 9 SCLK / 10 SCLK / 11 SCLK / 12 SCLK / 13 SCLK / 14 SCLK / 15 SCLK / 16 Ver1.2 4.40 3.67 3.14 2.75 2.44 2.20 2.00 1.83 1.69 1.57 1.47 1.38 4.80 4.00 3.43 3.00 2.67 2.40 2.18 2.00 1.85 1.71 1.60 1.50 3.2 ADC Clock Setting The IA/IB/VA input ADC clock will be set as 1/2 system clock.
Arch Meter Corporation 0111 1000 1001 1010 1011 1100 1101 1110 1111 PS1000 Ver1.2 ADC_CLK / 384 ADC_CLK / 544 ADC_CLK / 1088 ADC_CLK / 512 ADC_CLK / 1024 ADC_CLK / 136 ADC_CLK / 272 ADC_CLK / 128 ADC_CLK / 256 31.25K 22.06K 11.03K 23.44K 11.72K 88.24K 44.12K 93.75K 46.88K 28.65K 20.22K 10.11K 21.48K 10.74K 80.88K 40.44K 85.94K 42.97K In the PS1000, it still has one ADC for temperature measurement. This ADC can be controlled by the SARCFG.
Arch Meter Corporation 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 PS1000 Ver1.2 SYSCLK / 40 SYSCLK / 42 SYSCLK / 44 SYSCLK / 46 SYSCLK / 48 SYSCLK / 50 SYSCLK / 52 SYSCLK / 54 SYSCLK / 56 SYSCLK / 58 SYSCLK / 60 SYSCLK / 62 SYSCLK / 64 46.2 44.0 42.0 40.1 38.5 36.9 35.5 34.2 33.0 31.8 30.8 29.8 28.8 42.3 40.3 38.5 36.8 35.3 33.8 32.5 31.3 30.2 29.2 28.2 27.3 26.4 3.
Arch Meter Corporation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PS1000 SCLK / 1 SCLK / 2 SCLK / 3 SCLK / 4 SCLK / 5 SCLK / 6 SCLK / 7 SCLK / 8 SCLK / 9 SCLK / 10 SCLK / 11 SCLK / 12 SCLK / 13 SCLK / 14 SCLK / 15 SCLK / 16 PS1000Rev. 1.2 May 2006 22.00 11.00 7.33 5.50 4.40 3.67 3.14 2.75 2.44 2.20 2.00 1.83 1.69 1.57 1.47 1.38 12/ 67 Ver1.2 24.00 12.00 8.00 6.00 4.80 4.00 3.43 3.00 2.67 2.40 2.18 2.00 1.85 1.71 1.60 1.50 www.archmeter.
Arch Meter Corporation PS1000 Ver1.2 4. SFR Mapping The PS1000 has some non-standard SFR configure register for some special blocks, like, SPI, I2C, SSP, ALU and extended interrupt controller. The mapping of the PS1000 SFR is shown as follow. The red mark means these SFR were not the standard SFR.
Arch Meter Corporation PS1000 Ver1.2 reference table ALU I2C SSP SPI Interrupt ALU_OP, A0, A1, A2, A3, B0, B1, B2, B3 I2CCKH, I2CCKL, I2CCON, I2CSTA, I2CADR, I2CDAT SSPCON, SSPCFG SPICON, SPISTA, SPIDAT IMR, IPR, ICR, IRR PS1000Rev. 1.2 May 2006 14/ 67 www.archmeter.
Arch Meter Corporation PS1000 Ver1.2 5. I/O Mapping For the XDATA memory, address 0xF000 to 0xFFFF is mapping to the DSP and some special control register. The address 0xF000 ~ 0xF3FF(1KB) is mapped to DSPROM address. MCU can access this address by setting MCUCFG.DSPROM as ‘1’. When MCUCFG.DSPROM is setting as ‘0’. This address can not be access. The address 0xFC00~0xFCFF (256 bytes) is mapped to the DSP data buffer and the 0xFE00~0xFE7F (128 bytes) is mapped to the I/O configuration.
Arch Meter Corporation PS1000 Ver1.2 0xFE7F I/O Space (128 Bytes) 0xFE00 0xFD00 DSP Buffer (256 Bytes) 0xFC00 0xF400 0xF000 DSP ROM (1K Bytes) Control by MCUCFG 0x3FFF 16KB XDATA 0x0000 PS1000Rev. 1.2 May 2006 16/ 67 www.archmeter.
Arch Meter Corporation PS1000 FE00h FE01h FE02h FE03h FE04h FE05h FE06h FE07h FE08h FE09h FE0Ah FE0Bh FE0Ch FE0Dh FE0Eh FE0Fh ADCVA_L ADCVA_H ADCIA_L ADCIA_H ADCIB_L ADCIB_H Temp_L Temp_H AGCGain FE10h FE11h FE12h FE13h FE14h FE15h FE16h FE17h FE18h FE19h FE1Ah FE1Bh FE1Ch FE1Dh FE1Eh FE1Fh RTCYear RTCMonth RTCDay RTCWeek RTCHour RTCMinutes RTCSec FE40h FE41h FE42h FE43h FE44h FE45h FE46h FE47h FE48h FE49h FE4Ah FE4Bh FE4Ch FE4Dh FE4Eh FE4Fh LCDDAT0 LCDDAT1 LCDDAT2 LCDDAT3 LCDDAT4 LCDDAT5 LCDDAT6 LCD
Arch Meter Corporation PS1000 Ver1.2 FE11h FE12h FE13h FE14h FE15h FE16h RTCMonth RTCDay RTCWeek RTCHour RTCMinutes RTCSec RTC Month result (1~12) RTC Day result (1~31) RTC Weak result (1~7) RTC Hour result (0~23) RTC Minute result (0~59) RTC Second result (0~59) Read only Read only Read only Read only Read only Read only FE18h FE19h FE1Ah LoopCnt_L LoopCnt_H DSPStatus DSP loop count (low byte) DSP loop count (high byte) DSP status register Read only Read only Read only PS1000Rev. 1.
Arch Meter Corporation PS1000 Ver1.
Arch Meter Corporation PS1000 Ver1.
Arch Meter Corporation PS1000 Ver1.2 6. DSP The PS1000 has one special design 32-bit DSP for the Power calculation. For this DSP, it can perform and special program which define by the customer faster and lower power. The program for this DSP is shown below.
Arch Meter Corporation PS1000 Ver1.2 In the DSP, it had 64x32 memory space for DSP calculation. When the DSP finish the calculation base on the ADC sample number which specified by the sample count, the DSP will copy this memory data to the DSP output buffer (0xFC00 ~ 0xFCFF). The MCU can access this memory to get the DSP calculation result.
Arch Meter Corporation PS1000 Ver1.2 6.2 AGC The DSP circuit has built-in one AGC control circuit. It can control the AGC at the front of IA/IB ADC input. The control range is 1X, 2X, 4X and 8X.
Arch Meter Corporation PS1000 Ver1.2 The MCU can disable the AGC function and control by MCU itself. The MCUCFG can set the AGCCFG.EN as 0. It will disable the AGC function and the gain will follow the value by AGCCFG.IAGain and AFGCFG.IBGain. The MCU can get the current gain information form the AGCGain register. Here is the format of AGCGain. AGCGain (FE08h) B7 B6 0 0 B5 B4 B3 0 IAGain B2 0 B1 B0 IBGain The MCU can set the AGC threshold to control the AGC adjustment point.
Arch Meter Corporation PS1000 Ver1.2 7. MCU The PS1000 has one high performance 8-bit 8051 MCU. This MCU has 64KB program space and 16KB data space. It also has 256B internal data space. The PS1000 MCU is fully compatible with general purpose 8051 MCU. Except the stand MCU, the PS1000 MCU still have some more special functional block for the performance and I/O enhancement. For the standard MCU parts, please reference the 8051 user’s manual. The following description only focus on the different parts.
Arch Meter Corporation PS1000 Ver1.
Arch Meter Corporation PS1000 Ver1.2 Normal Operation Mode FFFFh FC00h FFFFh 1KB I/O Memory 64KB External Program Memory Internal 8051 7FFFh 32KB 3FFFh Shadow RAM (Prog.) 16KB 00FFh 0080h SFR 0000h 256B IDATA RAM XDATA RAM EA = 1 EA = 0 ICP Mode FFFFh FC00h FFFFh 1KB I/O Memory 64KB External Program Memory Internal 8051 7FFFh 00F 0080 0000 SFR 256B IDATA RAM 32KB Shadow RAM 07FFh 2KB Internal Program ROM EA = 1 PS1000Rev. 1.2 May 2006 27/ 67 EA = 0 www.archmeter.
Arch Meter Corporation PS1000 Ver1.2 External CPU Mode FFFFh FC00h 1KB I/O Memory External 7FFFh MCU 32KB Shadow RAM PS1000Rev. 1.2 May 2006 28/ 67 www.archmeter.
Arch Meter Corporation PS1000 Ver1.2 The mode setting quick reference table is shown as below.
Arch Meter Corporation PS1000 Ver1.2 8. SPI The PS1000 has one SPI interface which can be master or slave. This SPI interface is controlled by the SPICTL/SPIDAT/SPISTA register. These registers are mapped at the SFR memory space.
Arch Meter Corporation SPISTA(SFR 0xBE) B7 B6 SPIF WCOL SPIF WCOL MODF B5 MODF PS1000 B4 x Ver1.
Arch Meter Corporation PS1000 Ver1.2 For the SPI interface, it can select the different clock phase and polarity. Here is the timing diagram to show the different configuration.
Arch Meter Corporation PS1000 Ver1.2 CPHA = 1 PS1000Rev. 1.2 May 2006 33/ 67 www.archmeter.
Arch Meter Corporation PS1000 Ver1.2 9. I2C The PS1000 has one I2C interface. This I2C interface is controlled by the I2CCKH/I2CCKL/I2CCTL/I2CSTA/I2CDAT registers. These registers are mapped at the SFR memory space.
Arch Meter Corporation PS1000 Ver1.2 9.1 Registers The micro-controller interfaces with the I2C-bus through six Special Function Registers (SFRs): I2CCKHR (I2C SCL Duty Cycle Register High Byte), I2CCKLR (I2C SCL Duty Cycle Register Low Byte), I2CCTLR (I2C Control Register), I2CSTAR (I2C Status Register), I2CADRR (I2C Slave Address Register), and I2CDATR (I2C Data Register). I2CCKHR (I2C SCL Duty Cycle Register High Byte) I2CCKHR(SFR 0xB2) Reset value: 23h B7 B6 B5 B4 B3 B2 B1 B0 CKHR.7 CKHR.6 CKHR.
Arch Meter Corporation PS1000 Ver1.2 0 – 400 KHz. Thus the values of I2CCKHR and I2CCKLR have some restrictions. Some relationship between the system clock, bit data rate, and values of registers are shown in table 1-1. Note that the values for both registers greater than three system clocks are recommended.
Arch Meter Corporation I2CCTLR7 I2CEN I2CCTLR6 STA I2CCTLR5 STO I2CCTLR4 SI I2CCTLR3 AA I2CCTLR2-0 - PS1000Rev. 1.2 May 2006 PS1000 Ver1.2 I2C enable bit 1 = enables the I2C interface 0 = disables the I2C interface Start flag 1 = I2C enters master mode and generates a START condition. When the I2C interface is already in master mode and some data has been transmitted or received, it transmits a repeated START condition.
Arch Meter Corporation PS1000 I2CSTAR (I2C Status Register) I2CSTAR(SFR 0xB5) Reset value 00h B7 B6 B5 B4 STAR.4 STAR.3 STAR.2 STAR.1 Ver1.2 B3 STAR.0 B2 0 B1 0 B0 0 This register contains the status code of I2C interface. The least three bits are always zero. There are 26 possible status codes. When the code is 00H, there is no relevant information available and SI bit is not set. All other 25 status codes correspond to defined I2C states. When any of these statuses entered, the SI bit will be set.
Arch Meter Corporation PS1000 Ver1.2 I2CDATR register contains the data to be transmitted or the data received. The micro controller can read and write to this 8-bit register while it is not in the process of shifting a byte. Thus this register should only be accessed when the SI bit is set. Data in I2CDATR remains stable as long as the SI bit is set.
Arch Meter Corporation PS1000 Ver1.2 condition is transmitted, the SI bit is set, and the status code in I2C Status Register (I2CSTAR) should be 08h. This status code must be used to vector to an interrupt service routine where the user should load the slave address and data direction bit (SLA + W) to the I2C Data Register (I2CDATR). The I2C Status Register (I2CSTAR) must be cleared by firmware, thus the SI bit is automatically cleared, before the data transfer can continue.
Arch Meter Corporation S PS1000 Slave Address R A Ver1.2 Data A Data A/~A P Data Transfer (n Bytes + Acknowledge) "0" = Write "1" = Read A = Acknowledge (SDA low) ~A = Not Acknowledge (SDA high) S = START Condition P = STOP Condition From Master to Slave From Slave to Master Format of master receiver mode After a repeated START condition, I2C may switch to the Master Transmitter Mode.
Arch Meter Corporation PS1000 Ver1.2 the direction bit is 1 (R), it will enter Slave Transmitter Mode. After the address and the direction bit have been received, the SI bit is set and a valid status code can be read from the I2C Status Register (I2CSTAR).
Arch Meter Corporation PS1000 Ver1.2 9.3 Status Codes In this section, the appropriate action to be taken for each status code is shown below.
Arch Meter Corporation 30H 38H PS1000 Data byte in I2C has Load data byte been transmitted; No I2CDATR NACK has been action received No I2CDATR action Ver1.
Arch Meter Corporation PS1000 Ver1.
Arch Meter Corporation PS1000 Ver1.
Arch Meter Corporation 98H A0H PS1000 Ver1.2 Previously addressed Read data byte with general call, data has been received, NACK has been Read data byte returned 0 0 0 0 0 0 0 1 Read data byte 1 0 0 0 Read data byte 1 0 0 1 No I2CDATR action 0 0 0 0 No I2CDATR action 0 0 0 1 No I2CDATR action 1 0 0 0 No I2CDATR action 1 0 0 1 STOP condition or RESTART condition has been received while still addressed as slave PS1000Rev. 1.
Arch Meter Corporation PS1000 Ver1.
Arch Meter Corporation PS1000 Ver1.2 10. SSP The PS1000 has one SSP interface. This interface is compatible with TI serial peripheral interface specification. This SSP interface is controlled by the SSPCFG / SSPCKL / SSPDXR / SSPRXR / SSPSTA registers. These registers are mapped at the SFR memory space.
Arch Meter Corporation PS1000 CKEN Ver1.
Arch Meter Corporation PS1000 Ver1.2 The following diagram shows the SSP output waver under the DSP control mode. CLK FS DATA XX 5AA5 PS1000Rev. 1.2 May 2006 XX XX 0_GIA_F_GIB XX 51/ 67 VA XX IA XX IB www.archmeter.
Arch Meter Corporation PS1000 Ver1.2 11. RTC The PS1000 has one RTC (Real-Time Clock) circuit. It can keep one clock count reference base one 32.768 KHz crystal. This RTC circuit can make a different configuration base on the RTCCFG register.
Arch Meter Corporation PS1000 Ver1.2 RTCFADJ[3:0] RTC clock tuning fraction part (RTCAdj) 0000RTCAdj - 0/16Hz 0001RTCAdj - 1/16Hz 0010RTCAdj - 2/16Hz 0011 RTCAdj - 3/16Hz 0100RTCAdj - 4/16Hz 0101RTCAdj - 5/16Hz 0110 RTCAdj - 6/16Hz 0111 RTCAdj - 7/16Hz 1000RTCAdj - 8/16Hz 1001RTCAdj - 9/16Hz 1010RTCAdj - 10/16Hz 1011 RTCAdj - 11/16Hz 1100 RTCAdj - 12/16Hz 1101 1110 1111 RTCAdj - 13/16Hz RTCAdj - 14/16Hz RTCAdj - 15/16Hz The RTC clock information can read from several RTC registers.
Arch Meter Corporation PS1000 Ver1.2 For RTCWeek, the value will be 0 ~ 6. It is represent as Sunday to Saturday. The RTCWeek will not relative to which Year, Month and Day. It must set by user. The RTC circuit will keep the Week counting when the Day count is updated. RTCWeek(0xFE13) B7 B6 x x B5 x B4 x For RTCHour, the value will be 0 ~ 23. RTCHour(0xFE14) B7 B6 B5 B4 x x x B3 x B2 B1 Week (0~6) B3 B2 Hour (0 ~ 23) B0 B1 B0 For RTCMinute, the value will be 0 ~ 59.
Arch Meter Corporation PS1000 Ver1.2 12. LCD The PS1000 has build-in one LCD driver. It can driver one 40x4 LCD panel. This LCD circuit is controlled by setting the LCDCFG and LCDDIV register.
Arch Meter Corporation PS1000 Ver1.2 User can set the LCD display data at the LCD buffer from LCD0 ~ LCD19. The LCD controller will automatic load the LCD0~LCD19 data and display on the LCD screen. The LCD controller also has one LCD bias circuit. It can generate the LCD bias for the COM and SEG driving. User can change the bias voltage for 1/2, 1/3 or 1/4 bias control. Here is the bias circuit block diagram.
Arch Meter Corporation PS1000 Ver1.2 13. Interrupt The PS1000 has 8 extended interrupt input source for the SPI, I2C, SSP and I/O interface. The extended interrupt block diagram is shown as figure 2. IPR/ICR SPI_INT INT0/INT 1 T/C 0/1/2 I2C_INT TXINT ISR Entrycontrol Point I The extended interrupt control can be controlled by the 4 interrupt 8051 I R RXINT registers which are map to the SFR. That is IMR/ICR/IPR/IRR. Each bit of Interrupt R R TIin_2 IMR/IPR/ICR/IRR is mapped to an interrupt source.
Arch Meter Corporation Interrupt Type External INT0 Timer/Counter 0 External INT1 Timer/Count 1 Serial Port2 Timer/Counter 2 Extend INT Serial Port 1 PS1000Rev. 1.2 May 2006 PS1000 Ver1.2 Entry Point 8‘b00000011 (8’h03) 8'b00001011 (8’h0B) 8'b00010011 (8’h13) 8'b00011011(8’h1B) 8'b00100011 (8’h23) 8'b00101011 (8’h2B) 8'b00110011 (8’h33) 8'b00111011 (8’h3B) 58/ 67 www.archmeter.
Arch Meter Corporation PS1000 Ver1.2 14. Power Management In PS1000, it design a lot of power management control method. Most of the functional block can turn-on/off individually. The MCU/DSP/ADC also can operate on a lot of different clock rate. It is programmable by setting the clock diver counter. It can make the power management more easily. The following blocks have its own enable configuration setting.
Arch Meter Corporation PS1000Rev. 1.2 May 2006 PS1000 60/ 67 Ver1.2 www.archmeter.
Arch Meter Corporation PS1000 Ver1.2 15. PIN Mapping LQFP-128 Package Left Side Pin# Name Type Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I/O I/O Ground O I I I I Power (3.3V) I I O Ground Power (3,3V) I I I I I O Power (3.3V) Ground Power (3.3V) O I I I O O O O O 8051 P3 I/O port bit 6 (WR_) 8051 P3 I/O port bit 7 (RD_) Analog Ground Reference output IBM input IBP input IAP input IAM input 3.
Arch Meter Corporation PS1000 Ver1.2 Bottom Side 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 VCCK SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 GND SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 VCCK SEG29 PS1000Rev. 1.2 May 2006 O O O O O O Power(2.5V) O O O O O O O O O O O O Ground O O O O O O O O O O Power(2.
Arch Meter Corporation PS1000 Ver1.2 Right Side 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 VCCIO VCCK SO SCLK P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 VCCRTC RTCXI RTCXO RTCGND XTLO XTLI VCCK PS1000Rev. 1.2 May 2006 O O O O O O O O O O Power (3.3V) Power(2.5V) O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power(2.5V) I O Ground O I Power(2.
Arch Meter Corporation PS1000 Ver1.2 Top Side 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 VCCIO P2.5 SCL SDA GNDIO/GNDK P2.6 SI P2.7 P3.0 P3.1 P3.2 PSEN(P3.4) P3.3(P3.5) ALE SPICS VCCIO VCCK FSX DX CLK DR FSR PS1000Rev. 1.2 May 2006 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power (3.3V) I/O I/O I/O Ground I/O I I/O I/O I/O I/O I/O I/O I/O O Power (3.3V) Power(2.
Arch Meter Corporation PS1000 Ver1.2 Package Specification PS1000Rev. 1.2 May 2006 65/ 67 www.archmeter.
