User's Manual

USER MANUAL
WN7911A-LF
10
20 VDD_3.3V Power O
Internal PALDO output or feedback of output
from external PNP
21 GPIO_0 Signal I/O General-purpose interface pins.
22 VDD_2.5V Power O 2.5V LDO2p5 output
23 GND Power I Ground
24 VLX Power O Core buck regulator: Output to inductor
25 VIN_3V_5V Power I
Battery supply input for PALDO;
Core buck regulator: Battery voltage input
26 GPIO_2 Signal I/O General-purpose interface pins.
27 GND Power I Ground
28 SDIO_CLK Signal I/O SDIO clock
29 GPIO_3 Signal I/O General-purpose interface pins.
30 SDIO_DATA_0 Signal I/O SDIO data line 0
31 GPIO_1 Signal I/O General-purpose interface pins.
32 SDIO_DATA_1 Signal I/O SDIO data line 1
33 SDIO_DATA_2 Signal I/O SDIO data line 2
34 GPIO_9 Signal I/O General-purpose interface pins.
35 RESETn Signal I
Low asserting global chip reset: digital input
pin.
Used by PMU to enable/disable power the
internal regulators.
36 SDIO_CMD Signal I/O SDIO command line
37 SDIO_DATA_3 Signal I/O SDIO data line 3
38 VDDIO Power I
Digital I/O supply (1.8V to 3.3V)
VDDIO should be supplied externally;
SDIO I/O supply (1.8V to 3.3V)
39 GND Power I Ground