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BIOS
3.5 Advanced Chipset Features
CAS Latency Time
It allows CAS latency time in HCLKs as 2 or 2.5. The system board designer
should set the values in this eld, depending on the DRAM installed. Do not
change the values in this eld unless you change specications of the installed
DRAM or CPU.
Setting: 2.5 (Default), 2.
Interleave Select
It allows you to Use the Interleave Select option to specify how the cache
memory is interleaved.
Setting: LOI (Default), HOI.
XOR BA0
Setting: Disabled (Default), Enabled.
XOR BA1
Setting: Disabled (Default), Enabled.