Technical Manual

APPLIED TECHNOLOGY SOLUTIONS, INC.
Document: FCC1225manual.wpd issued: jan99 revised: July 27, 1999 page: 7
descrambler removes the scrambler key stream from the baseband data signal to recover the CVSD RX data signal. This
signal is output from the FPGA to the CVSD decoder. The decoder converts this data stream to an analog audio signal.
The audio output from the CVSD decoder is lowpass filtered to remove high frequency switching
components. The Model 1225 has two audio amplifiers. One drives the internal speaker, while the other is used with the
external speaker/microphone. A common volume control sets the gain of both amplifiers. The power on/off switch is
integrated with the volume control.
All other controls, PTT, CODE, and CHANNEL, interface directly with the FPGA. The voltage monitor
and activity detector also provide inputs to the FPGA. The FPGA generates the channel, code and T/R control signals based
on the status of the front panel controls, and it drives the PWR LED.
The voltage monitor checks the battery voltage and sends a signal to the FPGA if the voltage gets too low.
The FPGA contains logic that will blink the PWR LED indicating low battery voltage.
The activity detector measures the amplitude of the 2
nd
IF signal. Once a minimum threshold is passed,
it sends a signal to the FPGA. The FPGA responds by taking the data demodulator out of power-down mode. The
demodulator is powered-down during idle periods to conserve battery capacity.
Drive for the TX LED is taken from the switched DC power output from the power control. The power
control switches based on the status of the T/R signal from the FPGA.
3.1.2 RF/IF Section
During transmit, the two biphase modulated signals from the FPGA are individually bandpass filtered,
and then added together, to produce the baseband composite spread spectrum signal. This signal is up-converted at the first
TX mixer. The output from the first TX mixer is bandpass filtered by the IF band split filters. The outputs from these filters
are summed together by the IF combiner to produce the composite IF signal. The IF bandpass filter section is used for both
transmitting and receiving. The signal source for the filters is switched by the IF T/R switch.
The composite IF signal is up-converted to the final transmit frequency by the TX up-converter mixer.
The output of the TX up-converter mixer is bandpass filtered and amplified to drive the RF power amplifier. For economy,
the bandpass filter used here is shared between the transmit and receive signal paths using RF switches controlled by the
T/R signal. The RF switches isolate the transmit and receive signal paths to prevent interference.
The power amplifier is connected to the antenna through the antenna T/R switch. The status of this switch
is controlled by the T/R signal from the FPGA.
Received signals from the antenna go through the antenna T/R switch to the LNA (Low Noise Amplifier).
The output of the LNA is bandpass filtered by the shared channel filter. An RF amplifier stage follows the filter and drives
the RX down-converter mixer. The down-converter mixer output signal frequency is the same as transmit signal frequency.
Additional signal gain is provided by the IF amplifier.
In receive mode, the IF T/R switch connects the output of the IF amp to the IF band split section. Here,
the received spread spectrum signal is separated into its composite parts, the spread data and PN signals. These signals drive
the despreader mixer which produces a BPSK at the 2
nd
IF frequency. This signal is further amplified and filtered, prior to
going to the FPGA for demodulation.
Receive AGC control for the RF and first IF amplifiers is generated from the composite IF signal by the
AGC generator. The AGC loop maintains a fixed signal level at the despreader output.
Channel switching is accomplished by changing the frequency of the local oscillator that drives the TX
up-converter mixer and the RX down-converter mixer. The output from the local oscillator is shared between the two