Specifications

4 - Power Mac G5 Troubleshooting
General Information
Block Diagram
The architecture of the Power Mac G5 computer is based on the PowerPC G5
microprocessor and two custom ICs: the U3 memory controller/bus bridge and the K2 I/O
controller.
1.5 Gbps
Serial ATA bus
1 1  1  
  er e p r
 pi al au i  u S  
Air  r a e  a p r
   
 er
bus
1   
buses
 pi al au i i S  
 ire ire  pr r
1 bi
. Gps
  per
Tra sp r
 bi
1. G ps
  per
Tra sp r
   

bus
  AG  r sl 
 .1 G ps
   sl s
 
p  er
   r ller


   e sl 
IS
 S  . p r r  
  bps
 S  . p r rear
  bps
 S  . p r rear
  bps
   sl s
 er al  ar  ri e
ers
 ire ire  pr  rear
 ire ire  pr  rear
Main logic board
ATA1  bus
1  bps  S
1  bps
S
1.5 Gbps
Serial ATA bus
 er al  pi al
rie er
 er al
spea er
Air  r   re e
 ar sl 

er
   r ller
a  
bus bri  e

  e i e
a is
   r ller
 eape a
A al  li e u
A al  li ei
 ire ire

Au i
 ir uir
 lue  
    S
   r ller
 roc   or  od l
 roc   or  od l
  bi    er  G5
 i r pr  ess r
1   
1   
1   
  
bri  e
  bi  u  bi i   bi i   bi  u
 lue   a e  a p r
  bi    er  G5
 i r pr  ess r