Technical information

CHAPTER 2

Hardware Design

Processor and Memory System

In addition, the 84035 contains the PC/AT-compatible DMA channels and the system

arbitration logic for DMA masters and local bus masters. Those functions are needed by

the sound expansion card.

Clocks 2

The 84035 data path controller IC receives a 14.31818 MHz clock signal and divides it by

12 to form the 1.19 MHz clock used by the 8254 timers. In addition, the 84035 receives a

32.768 kHz clock signal for the internal real-time clock. All CPU related functions are

based on the 1X clock generated by the 84031 memory controller IC.

System Reset 2

The 84035 data path controller IC generates the reset signals for the DOS Compatibility

Card. The 84035 generates the SYSRESET and CPURESET signals based on the

/PWRGOOD signal from the Pretzel Logic IC. The CPURESET signal is also affected by

soft reset requests received over the control link from the 84031.

The /PWRGOOD signal controls several other signals. It disables all outputs and gates

off all inputs to the 84035 except for the /PWRSTB signal (PRAM, RTC power), the

14 MHz clock (14.31818 MHz input), the 32 kHz clock (32.768 kHz input), and the

/PWRGOOD signal itself. When the /PWRGOOD signal goes high, the outputs are

enabled and the SYSRESET and CPURESET signals are driven high. The 84035 holds the

SYSRESET and CPURESET signals high for 8 million cycles of the SCLK clock to ensure

proper startup of the 14.31818 MHz oscillator and to allow time for the VCO in the 80486

to stabilize.

The SYSRESET and CPURESET signals are generated as follows: The SYSRESET signal is

generated based on the /PWRGOOD signal alone. The CPURESET signal is generated

based on /PWRGOOD but is also generated for soft resets. Soft resets can occur due to a

keyboard controller reset, a CPU shutdown cycle, or the transition of bit 0 of port 92 in

the 84035 from a 0 to a 1.

Keyboard reset and shutdown are sent to the 84035 data path controller through the

control link from the 84031 memory controller, which decodes shutdown cycles and

receives keyboard reset from the 8242 keyboard controller.

The 84035 data path controller IC generates the /A20M signal to the 80486 micro-

processor. The 84035 generates the /A20M signal by ORing together the GATEA20 signal

from the keyboard controller and bit 1 of port 92 in the 84035. The keyboard controller’s

GATEA20 information comes from the 84031 memory controller through the control link.

Interrupt Control 2

The 84035 data path controller IC contains two 8259-compatible interrupt controllers.

The interrupt priorities are listed in Table 2-2 on page 17.