Technical information

CHAPTER 2
Hardware Design
Processor and Memory System 17
When the 80486 performs a misaligned write, the interface IC (Pretzel Logic) first checks
to see if the transfer is an aligned transfer on the Macintosh host computer. If it is, the
write is allowed to proceed. If the write is misaligned with respect to the host computer
(for example, a 3-byte transfer, or a 2-byte transfer that does not fall on a word
boundary), the interface IC forces the 80486 to break the transfer into multiple single-
byte operations. This ensures that misaligned transfers on the PC side get mapped to the
proper addresses in the host computer’s memory.
Interrupts 2
The 84031 and 84035 ICs, described in later sections, are responsible for generating all
interrupt requests to the 80486 microprocessor. The 84035 data path controller IC
generates the maskable interrupt resulting from the various IRQ sources. For interrupt
functions, the 84035 is equivalent to two cascaded 8259 interrupt controllers (PIC) as
found in the original PC/AT. Table 2-2 shows the interrupt definitions for the PC on the
DOS Compatibility Card.
The source of the PDS non-maskable interrupt (SLOT_E signal) is the Pretzel Logic IC
(described on page 26). With the exception of transfers in which the PDS becomes
bus master, all service between the PC side and the Macintosh host computer is
interrupt driven.
The master interrupt status register in the Pretzel Logic IC contains the state of all
interrupt sources on the card. Each of these interrupt sources can be individually masked
by an accompanying master interrupt enable register. Additionally, higher resolution
Table 2-2 Definitions of PC interrupts
Interrupt
number Description
0 Interval timer
1 Keyboard and mouse
2 PIC 2
3* COM2 port*
4* COM1 port*
5 Sound expansion card
6* Message mailbox*
7* Parallel port 1*
8 Real time clock
12 Auxiliary port
NOTE
Asterisk (*) indicates interrupt requests
with source in the interface (Pretzel Logic) IC.