Technical information

CHAPTER 2

Hardware Design

Processor and Memory System

Table 2-1 describes the different transfer sizes supported by the PowerPC 601 and the

80486. The table also identiﬁes the 68040 transfers, which are a subset of the

PowerPC 601 transfers.

All accesses in the Macintosh environment are longword aligned: the low-order 2 bits of

the address are zeros. Each time the 80486 performs a 1-, 2-, 3-, or 4-byte access, the

Macintosh host computer performs a 4-byte access. The full 32 bits of data are presented

on the PC side and the 80486 accepts the required byte lanes. When the 80486 requests

multiple bytes of data from a nonaligned address (that is, when the data extends across a

longword address), the 80486 splits the access into two separate transfers.

Table 2-1

Transfer size comparison

Transfer size PPC 601 bytes enabled 80486 bytes enabled

1 byte 7 0

3* 3

2* 2

1* 1

0* 0

2 bytes 7, 6 0, 1

5, 4 2, 3

— 1, 2

3, 2* 0, 1

1, 0* 2, 3

3 bytes 7, 6, 5 1, 2, 3

6, 5, 4 0, 1, 2

5, 4, 3 1, 2, 3

4, 3, 2 0, 1, 2

3, 2, 1 1, 2, 3

2, 1, 0 0, 1, 2

4 bytes 3, 2, 1, 0* 0, 1, 2, 3

7, 6, 5, 4 0, 1, 2, 3

8 bytes 7, 6, 5, 4, 3, 2, 1, 0 not supported

NOTE

Asterisk (*) indicates byte transfers supported on the 68040.