Technical information

CHAPTER 2
Hardware Design
Processor and Memory System 15
Cache Snooping 2
The 80486 cache supports bus snooping to track activity on the bus that alters the
memory represented in the internal cache. However, no alternate master exists on the PC
system bus in the DOS Compatibility Card, so the snoop control lines are deactivated.
The memory space reserved for the PC (whether local or shared memory) cannot be
cached or modified by the Mac OS, so it presents no coherency issues.
The interface provides no hooks to support bus snooping in either the PC environment
or the Macintosh environment.
Byte Order 2
Big-endian and little-endian are two ways of defining the order in which bytes are
addressed. Big-endian means that the most significant byte corresponds to the lowest
address and the least significant byte corresponds to the highest address. Little-endian
means that the most significant byte corresponds to the highest address and the least
significant byte corresponds to the lowest address.
The PowerPC microprocessors support big-endian byte addressing and the 80x86 family
uses little-endian byte addressing. This disparity poses a problem for the DOS
Compatibility Card because its 80486 microprocessor is dependent on the Mac OS to
load applications and data from peripheral devices. When the Mac OS loads PC data
from floppy disk, it stores that data at addresses that match the big-endian convention.
To allow the PC to function properly, it must be able to read the data just like the
Mac OS; that is, the transfer must be address invariant. To make that possible with the
disparity in addressing modes, the interface IC performs a byte swapping operation.
Byte swapping is performed for all PC data resident on the Macintosh host computer,
that is, for both shared memory data and DMA (I/O) data. The interface IC also swaps
the bytes of data in one of the message mailbox data registers. The other data register
does not provide for byte swapping and thus provides data invariance.
For more information about the two ways of addressing memory, please refer to
Appendix A, “Overview of PowerPC Technology,” in Macintosh Developer Note Number 8 .
Misaligned Transfers 2
Data misalignment occurs when the DOS Compatibility Card is configured for
shared memory.
Unlike the 68040, the PowerPC 601 has a 64-bit data bus that provides greater capability
for handling misaligned transfers. The PPC 601 defines misaligned transfers as those that
are not doubleword aligned, whereas the 68040 defines a misaligned transfer as one that
is not longword aligned. Because the interface IC (Pretzel Logic, described on page 26)
was originally designed to support a 68040 bus interface, misaligned transfers (3-byte
transfers) from the 80486 are broken into two transfer cycles and do not take advantage
of the PowerPC 601 microprocessor’s extended data bus.