Specifications

CHAPTER 3
I/O Specifications
54 XD Connector
28 SA(1) S address bit 1
30 SA(0) S address bit 0
31 DACK(3) DMA acknowledge 3
32 TC Terminate count
33 BALE Bus address latch enable
34 SA(2) S address bit 2
35 IOCHRDY I/O check ready
36 SA(8) S address bit 8
37 SA(5) S address bit 5
38 IRQ(10) Interrupt request 10
39 ATCLK AT clock
40 XD(0) Buffered data bit 0
41 SA(3) S address bit 3
42 +5 V +5 V power supply
43 SA(6) S address bit 6
44 XD(1) Buffered data bit 1
46 XD(2) Buffered data bit 2
47 XD(5) Buffered data bit 5
48 XD(3) Buffered data bit 3
49 XD(6) Buffered data bit 6
50 XD(4) Buffered data bit 4
Table 3-9 XD connector pin assignments (continued)
Pin number Signal Description