Specifications

CHAPTER 3
I/O Specifications
44 PCI Connector
Table 3-3 shows how the bus command and byte enable (CBE(3:0)) signals are encoded.
B40 Not connected
(PERR L)
On the 12" and 7" cards, this pin is not connected.
On the PCI bus, it is used for Parity Error, which
reports data parity errors during all PCI
transactions except special cycles.
B42 Not connected
(SERR L)
On the 12" and 7" cards, this pin is not connected.
On the PCI bus, it is used for System Error, which
reports address parity errors, data parity errors
during special cycles, and any catastrophic
system error.
B60 Not connected
(ACK64 L)
On the 12" and 7" cards, this pin is not connected.
On the PCI bus, Acknowledge 64-bit Transfer
indicates that the target device is able to transfer
data in 64-bit blocks.
Table 3-3 CBE(3:0) L encoding
CBE setting Command
Bit 3 Bit 2 Bit 1 Bit 0
0000Interrupt acknowledge
0001Special cycle
0010I/O read
0011I/O write
0100Reserved
0101Reserved
0110Memory read
0111Memory write
1000Reserved
1001Reserved
1010Configuration read (used at initialization)
1011Configuration write (used at initialization)
1100Memory read multiple
1101Dual address cycle
1110Memory read line
1111Memory write and invalidate
Table 3-2 PCI connector pin assignments (continued)
Pin number Signal Description