Specifications

CHAPTER 3
I/O Specifications
PCI Connector 41
B37 DEVSEL L This is the device select signal. When a device
has decoded the device address and recognizes
itself as the target of the current access, it outputs
this signal. The signal is input to the host,
indicating that a device on the bus has been
selected.
B39 LOCK L This is the lock signal and, when it is asserted, it
indicates that the operation may require multiple
transactions to complete. When LOCK L is
asserted, it locks the address that is currently
being accessed, but transactions that are not
exclusive may proceed to an address that is not
currently locked. When a master device is
granted access to the PCI bus, it is not
guaranteed control of the LOCK L signal.
Different agents may use the PCI bus, but only
one master has ownership of LOCK L. If a device
implements executable memory, it must also
implement LOCK L and guarantee exclusive
access to the memory block. The target for this
sort of access must guarantee exclusive access to
a minimum of 16 aligned bytes. Host bridges
must also implement LOCK L.
B44 CBE(1) L Bus command and byte enable signal 1. Refer to
the description for pin A52 for further
information.
B45 AD(14) Address/data bit 14.
B47 AD(12) Address/data bit 12.
B48 AD(10) Address/data bit 10.
B50, B51 — No pins with these numbers.
B52 AD(8) Address/data bit 8.
B53 AD(7) Address/data bit 7.
B55 AD(5) Address/data bit 5.
B56 AD(3) Address/data bit 3.
B58 AD(1) Address/data bit 1.
A12, A13, A18,
A24, A30, A35,
A37, A42, A48,
A56, B3, B12,
B13, B15, B17,
B22, B28, B34,
B38, B46, B49,
B57
GND On the 12” and 7” cards, these pins are connected
to ground. They are also generally connected to
ground on the PCI bus.
Table 3-2 PCI connector pin assignments (continued)
Pin number Signal Description