Specifications

CHAPTER 3
I/O Specifications
40 PCI Connector
A54 AD(6) Address/data bit 6.
A55 AD(4) Address/data bit 4.
A57 AD(2) Address/data bit 2.
A58 AD(0) Address/data bit 0.
B16 PCI CLK This PCI clock input supplies timing for all
transactions on the PCI bus. All other PCI signals,
with the exception of RESET L and
IRQ L, are sampled on the rising edge of
PCI CLK. The PCI bus typically operates at 33
MHz, with a minimum frequency of 0 Hz.
B18 REQ L The master device asserts this signal to request
access to the PCI bus. It is a point-to-point signal,
and each master has its own REQ L.
B20 AD(31) Address/data bit 31.
B21 AD(29) Address/data bit 29.
B23 AD(27) Address/data bit 27.
B24 AD(25) Address/data bit 25.
B26 CBE(3) L Bus command and byte enable signal 3. Refer to
the description for pin A52 for further
information.
B27 AD(23) Address/data bit 23.
B29 AD(21) Address/data bit 21.
B30 AD(19) Address/data bit 19.
B32 AD(17) Address/data bit 17.
B33 CBE(2) L Bus command and byte enable signal 2. Refer to
the description for pin A52 for further
information.
B35 IRDY L This is the initiator-ready signal. When it is
asserted, it indicates that the bus master, in this
context the Macintosh computer, is able to
complete the current data phase of the bus
transaction. If a write cycle is in progress,
TRDY L going active (low) indicates that valid
data is present on the AD(31:0) lines. When
TRDY L goes active during a read cycle, it
indicates the master is prepared to accept data. A
data phase is completed during any clock cycle
where both TRDY L and IRDY L are active. If one
signal is active before the other, wait cycles are
inserted until both signals are active at the same
time.
Table 3-2 PCI connector pin assignments (continued)
Pin number Signal Description