Specifications

CHAPTER 3
I/O Specifications
PCI Connector 39
A36 TRDY L This is the target-ready signal. When it is
asserted, it indicates that the selected device, in
this context the 12” or 7” card, is able to complete
the current data phase of the bus transaction. If a
write cycle is in progress, TRDY L going active
(low) indicates that valid data is present on the
AD(31:0) lines. When TRDY L goes active during
a read cycle, it indicates the master is prepared to
accept data. A data phase is completed during
any clock cycle where both TRDY L and IRDY L
are active. If one signal is active before the other,
wait cycles are inserted until both signals are
active at the same time.
A38 STOP L When this stop signal is asserted, it means that
the target device is requesting the bus master to
stop the current transaction.
A43 PAR This is the parity bit for AD(31:0). All devices on
the PCI bus, in this context the 12” and 7” cards,
must generate parity. Parity is even for these
devices. PAR is stable one clock after the address
phase. During write transactions, this is one clock
after IRDY L is asserted, and during read
transactions, it is one clock after TRDY L is
asserted. PAR remains valid for one clock cycle
after the completion of the last data phase. The
master drives PAR during address and write data
phases, and the target drives PAR during read
data phases.
A44 AD(15) Address/data bit 15.
A46 AD(13) Address/data bit 13.
A47 AD(11) Address/data bit 11.
A49 AD(9) Address/data bit 9.
A50, A51 — No pins with these numbers.
A52 CBE(0) L Bus command and byte enable signals (C or BE)
are multiplexed on this pin. Pins B26, B33, and
B44 carry the other three signals that make up
this group. During the address phase of a bus
transaction, CBE(3:0) L define the bus
commands. Table 3-3 on page 44 shows how
these signals are encoded during a bus
transaction.
During the data phase, the signal(s) enable the
selected byte. For example, when CBE(0) L is
driven low, byte 0 is enabled. The byte enable
signals remain active throughout the data phase.
Table 3-2 PCI connector pin assignments (continued)
Pin number Signal Description