Specifications

CHAPTER 3
I/O Specifications
38 PCI Connector
Table 3-2 PCI connector pin assignments
Pin number Signal Description
A6 IRQ L This is a maskable interrupt request resulting
from various IRQ sources. Use of interrupts is
optional on the PCI bus.
A15 RESET L This is the reset signal. When it is driven low, all
PCI registers, sequences, and signals are reset to a
consistent state. If the signals are tristate, this
means that they are returned to the tristate (off)
condition.
A17 GNT L This is the grant signal. When a master device
requests access to the PCI bus, this signal is
asserted to indicate that access has been granted.
It is a point-to-point signal, and each master has
its own GNT L.
A20 AD(30) Address/data bit 30.
A22 AD(28) Address/data bit 28.
A23 AD(26) Address/data bit 26.
A25 AD(24) Address/data bit 24.
A26 IDSEL L This is the initialization device select signal.
When memory chips are being initialized by
configuration read and write transactions, this
signal is used to select individual ICs.
A28 AD(22) Address/data bit 22.
A29 AD(20) Address/data bit 20.
A31 AD(18) Address/data bit 18.
A32 AD(16) Address/data bit 16.
A34 FRAME L This is the cycle frame signal. A bus transaction
begins when this signal is asserted (driven low)
by the master. The first clock cycle during which
FRAME L is active is the address phase. This
means that the address/data lines, AD(31:00), are
carrying the physical address of the location to be
accessed. Data phases on the bus are controlled
by IRDY L and TRDY L. However, FRAME L
remains active throughout the bus transaction. It
is driven high (inactive) at the end of the final
data phase.