Specifications

CHAPTER 3
I/O Specifications
PCI Connector 37
With respect to the pin assignments and signal descriptions listed in Table 3-2, you
should note the following:
■ An “L” used as a suffix to the signal name, for example, FRAME L, indicates a signal
that is active when driven low. Signals with no suffix are active when they are driven
high.
■ In this context, the following terms are used to define the different components in the
system:
Agent indicates any entity that operates on the PCI bus.
Master indicates any agent that initiates a bus transaction.
A host bridge is a low latency path through which the processor may directly access
PCI devices that are mapped anywhere in memory, I/O, or configuration address
spaces.
Target indicates any agent that responds with a positive acknowledgment
(DEVSEL L) to a bus transaction initiated by the master.
■ The term tristate is applied to signals that are capable of three states: high, low, or off.
When the signal is off, it is said to be in a tristate condition or to be tristated.
■ Address bits 31:00 and data bits 31:00 (AD(31:0)) are multiplexed on the same PCI
pins. A bus transaction starts with the address phase followed by one or more data
phases. As described in the following table, certain control signals (FRAME L,
TRDY L, and IRDY L) determine the bus phase. AD(7:0) is the least significant byte,
and AD(31:24) is the most significant byte.
■ Groups of pins that are grounded, provide power inputs, or are not connected are
listed at the end of the table.
Timeout 5 bus clocks
Burst capability Any number of bytes
Power allocation 25 W per card for 12” card
15 W per card for 7” card
Table 3-1 PCI bus specifications (continued)
Feature Description