Specifications

CHAPTER 3
I/O Specifications
36 PCI Connector
Figure 3-3 PCI bus signals used in the 12” and 7” cards
Table 3-1 PCI bus specifications
Feature Description
Bus clock rate 33 MHz
Addressing Dynamic
Signal loading One load per signal
Transaction length determination Determined at end of transaction
Bus termination Not required
Bus control arbitration Centralized
Addressing spaces Memory, I/O, and configuration
Wait-state generators Slave and master
Kinds of expansion Cards and ASIC chips
AD[31:0]
ADCBE[3:0] L
ADPAR

ADPCICLK
ADRESET L

ADFRAME L
ADTRDY L
ADIRDY L
ADSTOP L
ADDEVSEL L
ADIDSEL L
ADLOCK L

ADREQ L
ADGNT L

ADPERR
ADSERR
Address
and data
Interface
control
System
Arbitration
Error
reporting
PCI
bus