Specifications
CHAPTER 2
Hardware Design
Hardware Features 19
12” Card Memory Control—DRAM and External Cache 2
Basic memory for the 12” card is provided by four 2 MB DRAMs that provide 8 MB of
memory. The DRAMs are organized as a 1-by-64-megabit memory bank (bank 0), as
shown in Figure 2-6.
The 12” card has a 168-pin DIMM slot that can accommodate DIMMs with
parity-checking capability. (The parity bits are not currently enabled.) You can use
DIMMs of different capacities in the slot (8 MB, 16 MB, 32 MB, or 64 MB), expanding
memory capacity up to 72 MB. This block of memory also has a 64-bit data path and is
addressed as bank 1.
The 12” card has 8 static RAMs that make up the 256 KB cache memory. Each static RAM
has an 8-bit data bus. The memory controller controls all transfers between the
microprocessor and the external cache. It generates the cache chip select signal, CCS L
7:0, and the read/write signal, ECAWE L. It buffers the control signals and drives them
out to the cache. It drives the cache address lines through external latches, which hold
the last address as the microprocessor generates the next address.
Figure 2-6 DRAM control—12” card
Pentium-class
microprocessor
PC chip set
82C558
PC chip set
82C556 memory
controller
32K
64-bit data bus
D(63:0)
To other devices
64-bit data bus
MD(63:0)
64-bit data bus
MD(63:32)
D(63:56)
D(55:48)
D(47:40)
D(39:32)
D(31:24)
D(23:16)
D(15:8)
D(7:0)
8 static RAMs provide
256KB cache memory
DIMM
2MB
2MB
2MB
2MB
4 DRAMs
MD(63:48)
MD(47:32)
MD(31:16)
MD(15:0)
Data bank 0
8-bit data buses
16-bit data buses
MD(63:0)
DIMMs up to
64 MB capacity
increase DRAM
capacity up to
72 MB