Specifications

18
Technology Overview
Xserve
channels for synchronized 256-bit memory transactions, further increasing perfor-
mance. By comparison, Xserve G5 systems have a 128-bit memory controller and use
400MHz DDR1 memory.
Memory capacity up to 32GB
Xserve provides twice the memory capacity—up to 32GB—of the Xserve G5. It also
accomplishes this at up to three times the bandwidth of the 400MHz DDR1 memory
in Xserve G5.
Advanced error protection
FB-DIMM technology offers higher reliability and better availability and serviceability.
That includes powerful, enhanced data ECC protection, such as single-bit error correc-
tion and detection of multiple-bit errors. It also includes various other complementary
high-availability features, such as ECC on-demand scrubbing, CRC on all transactions,
and SDDC algorithms to detect and correct a single device failure.
•
Error Correction Code protection with on-demand scrubbing. Automatically
detects a single-bit error when read from main memory and detects (but doesn’t
correct) multiple-bit errors. When a cache line is read from main memory and a single-
bit ECC error is detected, the memory controller will trigger an interrupt and log the
error (including the DIMM number, which remote monitoring tools will also display),
while automatically correcting it and passing its data along to the processor cache.
As part of the correction process, a hardware memory scrubber immediately rewrites
the value to correct the memory error in main memory. This feature prevents any
future read of the same memory location from taking an ECC interrupt and impacting
performance, while also trying to prevent a single-bit error from degenerating into a
multibit error.
•
Enhanced CRC (cyclic redundancy checking) protection. Checks the transfer of
all addresses, commands, and data, and automatically retries the transaction when
an error is detected, assuring uninterrupted operation in case of transient errors.
Without the advanced error detection capabilities of FB-DIMMs, errors like this would
halt the system.
•
Single Device Data Correction (SDDC). Typical ECC memory subsystems can over-
come single-bit errors only. Multiple-bit errors will panic and halt the system. Systems
that support Chipkill technology enhance data correction capabilities by being able
to deal with a single DRAM device failure if the DIMM is implemented with x4 DRAM
parts. The memory controller in Xserve builds on these memory availability features
by implementing an advanced error detection and correction algorithm called Single
Device Data Correction (SDDC). This algorithm not only supports traditional ECC
capabilities, but also detects and automatically corrects the failure of a single x4 or
x8 memory DRAM on a fully buffered DIMM. It also supports detection of a two-wire
fault on the DIMM connector or main logic board.
•
On-DIMM embedded diagnostics. The Advanced Memory Buffer (AMB) ASIC on
every FB-DIMM contains embedded diagnostics features, including error detection,
error injection, and Built-In Self-Test (BIST). The features do not provide error protec-
tion during system runtime; rather they allow for extensive and quick diagnostics
during system Power-On Self-Test (POST), during hardware testing with diagnostics
software, and during factory testing and system qualification. These capabilities help
ensure that system memory does not suffer from any hard failures in the AMB or
DRAM components, or from any communications problems between the FB-DIMM
and memory controller.
4GB DIMM support
Xserve supports 4GB DIMMs, allowing the
system to accommodate up to 32GB of
main memory.
Maximizing memory performance
Using four memory channels, Xserve can
use a 256-bit-wide memory architecture
to achieve bandwidth up to 21.3GB/s. For
the best system performance, memory
should be installed in sets of four identical
FB-DIMMs.