Specifications

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Technology Overview
Xserve
Dual Independent 1.33GHz Frontside Buses
Xserve features dual independent 64-bit frontside buses—one bus per processor—to
support a wide and fast path to system memory. The parity-protected buses feature
a unique power-saving capability that powers down part of the bus when full band-
width is not being utilized. Each channel runs at 1.33GHz independent of processor
speed; combined they provide up to 21.3GB/s bandwidth.
Advanced FB-DIMM Memory Technology
The fully buffered DIMM (FB-DIMM) is the next evolution in memory technology for
servers and workstations that value both capacity and bandwidth. With older memory
technologies, as signaling rates increase, the number of DIMMs supported per channel
decreases. The result has been a trade-off between overall memory capacity and band-
width. FB-DIMMs evade this trade-off by providing maximum capacity at the highest
bandwidth.
The FB-DIMM is based on a high-speed point-to-point interface that uses an Advanced
Memory Buffer (AMB) between the memory module and the memory controller.
With high-speed serial communications, the number of wires needed to connect
the chipset to the memory module is significantly lower. FB-DIMM memory channels
require just 69 pins from the memory controller, compared with 240 pins for tradi-
tional parallel DDR2 memory. This efficiency allows more memory channels from the
memory controller, increasing memory performance.
Previous memory technologies used a shared parallel interface with all DIMMs on the
same bus. The AMB decouples the memory interface from the DRAM components,
allowing the memory bus to run at high speed with more DIMMs. This also allows
simultaneous reads and writes using industry-standard DDR2 DRAM chips.
The comparison of FB-DIMM communications to parallel memory communications
is similar to the comparison of PCI Express communications to PCI or PCI-X parallel
communications. PCI Express and FB-DIMMs use high-speed serial interfaces for
communications and feature a reduced pin count and higher signaling rates. Both
provide separate channels for data transmission and data reception, supporting
simultaneous read and write operations. Both also provide higher bandwidth than
their predecessors, use fewer communications lines (pins), take less space on the
main logic board, and result in significantly greater system flexibility and increased
capability for the end user.
In addition, FB-DIMM technology offers greatly improved reliability, availability, and
serviceability (RAS) by complementing traditional ECC (Error Correction Code) data
protection with CRC (cyclic redundancy checking) protection of the entire data path
and an advanced SDDC (Single Device Data Correction) algorithm to enhance failure
correction. FB-DIMMs perform CRC on the transfer of all addresses, commands, and
data, and automatically retry when an error is detected. This allows for uninterrupted
operation in case of transient errors. SDDC is performed by the memory controller
to provide enhanced data protection and correction. The memory controller detects
and corrects single-bit errors with ECC, but with SDDC, it can also detect and correct
a complete failure of an x4 or x8 DRAM part on the FB-DIMM, as well as a two-wire
failure on the DIMM, DIMM slot, or main logic board.
Quad-channel 256-bit-wide memory controller
Xserve incorporates a new 256-bit-wide memory controller that allows for higher
speed, greater capacity, and improved reliability. Using fast 667MHz DDR2 FB-DIMM
memory gives an immediate boost to application performance. When sets of four
matched DIMMs are installed in Xserve, the memory controller utilizes all four memory
What is a fully buffered DIMM?
A fully buffered DIMM, or FB-DIMM, is a new
kind of high-performance computer mem-
ory module that helps increase a system’s
reliability, speed, and memory density while
keeping down costs. Based on a high-speed
point-to-point interface, it works with an
Advanced Memory Buffer ASIC that allows
full-speed, simultaneous reads and writes
using industry-standard DRAM chips.
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
Buffer
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
Buffer
System
Controller
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Differential
Pairs
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