Specifications

Vast amounts of addressable memory
The move to 64-bit processing results in a similarly dramatic leap in the amount of
memory supported. A memory address is a special kind of integer, which points to
one byte in memory. Since memory addresses are computed in 64-bit registers capable
of expressing integers up to 18 billion billion, the PowerPC G5 can theoretically address
16 exabytes (18 billion billion bytes) of virtual memory.
In practice, memory addressing is defined by the physical address space of the proces-
sor. The PowerPC G5, with 42 bits of physical address space, supports a colossal 2
42
bytes, or 4 terabytes, of system memory. Although it’s not currently feasible to purchase
4 terabytes of RAM, the advanced architecture of this processor allows for plenty of
growth in the future.
Multiple high-precision calculations
With 64-bit-wide data paths and registers, the PowerPC G5 can execute multiple
instructions on 64 bits of data—including huge integer calculations and double-
precision floating-point mathematics—in every clock cycle. In contrast, a 32-bit
processor has to split up any data larger than 32 bits and process it in multiple passes.
This leap in performance, from 32-bit to 64-bit processing, brings previously unmanage-
able tasks into the realm of practicality, facilitating highly accurate calculations required
for scientific analysis, technical research, 3D effects, and video encoding.
Next-Generation PowerPC Architecture
Apple and IBM built the PowerPC G5 processor for maximum efficiency and perfor-
mance. Its architecture features processing innovations that optimize the flow of data
and instructions, including a high-bandwidth execution core with dual floating-point
units and dual integer units. For more information about the PowerPC G5 architecture,
see www.apple.com/g5processor.
12
Technology Overview
Xserve G5
Support for more memory in
Mac OS X Server
Mac OS X Server makes the most of the
expanded memory capabilities of the
PowerPC G5. With up to 4GB of memory
allocated per application, each server task
can have dedicated space in the system’s
generous memory.
PowerPC G5 Architecture
The execution core contains 12 discrete
functional units:
• The Velocity Engine uses two large queues
and dedicated 128-bit registers for vector
processing.
• Two 64-bit double-precision floating-point
units provide the speed and accuracy required
for highly complex computations.
• Two 64-bit integer units perform calculations
for a broad range of computing tasks.
• Two load/store units manage data as it is
processed, keeping the processor’s large
registers filled for faster operations.
• The condition register stores the results of
branch predictions to improve the accuracy
of future predictions.
• The branch prediction unit uses innovative
three-component logic to maximize processor
efficiency.
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