Specifications

CHAPTER 3
Expansion
Expansion Slot 33
/CPU.BG Processor bus grant; signal from the external device can become bus master
following completion of current processor bus cycle.
D0–D31 Data lines.
/DS Data strobe. During read operation, /DS indicates that external device should place
data on data bus; during write operation, /DS indicates that the main processor has
placed valid data on the data bus.
/DSACK0,
/DSACK1
Data transfer acknowledge signals; indicate completion of data transfer operation
from main processor; inform the processor of the size of the data port.
FC0–FC2 Function code used to identify address space of current bus cycle.
/HALT Signal indicating that main processor should suspend all bus activity.
IPL0–IPL2 Interrupt priority-level lines.
/RESET Bidirectional signal that initiates system reset.
RMC Three-state output signal that identifies current bus cycle as part of indivisible
read-modify-write operation.
/R/W Read/write; three-state output signal that defines direction of bus transfer with
respect to the main processor.
SIZ0–SIZ1 Three-state output signals that work in conjunction with processor’s dynamic bus
sizing capabilities to indicate number of bytes remaining to be transferred during
current bus cycle.
/STERM Connected to the /STERM signal on the main processor; indicates termination of a
transfer using the MC68030 synchronous cycle.
Table 3-4 Expansion slot signals not connected to the MC68030
Signal name Signal description
CACHE Signal from the card, indicating that the current bus transaction can be satisfied by
the external cache on the card.
CLK16M Independent clock running at 15.6672 MHz; provided for compatibility with
Macintosh LC and LC II PDS cards.
CPU.CLK Main processor clock (25.0 MHz).
/CPU.DISABLE Disables the MC68030 CPU (and MC68882 FPU, if installed) on the main logic
board. This signal is used by a PDS card that replaces the main processor.
CPU.TYPE Defines bus protocol for the PDS; logical one (1) for MC68020 and MC68030, logical
zero (0) for MC68040.
continued
FC3 Additional function code bit, used to indicate that the software is running
in 32-bit address mode. (As in the Macintosh LC II, the software always runs in
32-bit mode.)
Table 3-3 Processor-direct expansion connector signal descriptions (continued)
Signal name Signal description