Specifications

CHAPTER 3
Expansion
32 Expansion Slot
All the signals on the expansion connector are capable of driving at least one TTL load
(1.6 mA sink, 400 µA source). Most of the signals are connected to other MOS devices on
the main logic board; for those signals, the DC load on the bus signals is small. The
high-order 16 data lines (D16–D31) have one LS load connected to them.
Descriptions of the Signals 3
Most of the signals on the expansion connector are connected directly to the signal of the
same name on the MC68030 microprocessor. Table 3-3 describes the functions of those
processor-direct signals. Table 3-4 gives the signal descriptions for the signals that are not
connected to the MC68030.
Table 3-2 Signals on the 18-pin section of the expansion connector
Pin
number Row A Row B Row C
35 A28 /CPU.BG CPU.CLK
36 A29 CPU.TYPE A30
37 /CIOUT /CPU.AS /STERM
38 /CBACK /CPU.DISABLE /CBREQ
39 /SLOTIRQ.D /DSACK0 /SLOTIRQ.C
40 CACHE GND /DSACK1
Table 3-3 Processor-direct expansion connector signal descriptions
Signal name Signal description
A0–A31 Address lines.
/BERR Bus error; bidirectional signal indicating that invalid bus operation is being
attempted.
/BGACK Bus grant acknowledge; input signal indicating that external device has become
bus master.
/BR Bus request; input signal indicating that external device is requesting to become
bus master.
/CBACK CPU burst acknowledge; used with /STERM during a burst transfer to indicate
that individual elements of a burst transfer are ready.
/CBREQ CPU burst request; used to initiate a quadruple longword burst transfer.
/CIOUT Cache inhibit out signal from main processor, indicating that a second-level cache
is allowed to participate in the current bus transaction.
/CPU.AS Processor’s address strobe; three-state output signal indicating that an active bus
transaction is occurring.
continued