Specifications

Developer Technical Support September 1989
Apple IIGS
#68: Tips for I/O Expansion Slot Card Design 5 of 6
The /DMA signal should be asserted and deasserted within the 100 nanosecond period after PH0
falls, and the DMA address should be emitted by the expansion card about 30 nanoseconds later.
In any case, the address should be stable on the address bus no later than 120 nanoseconds after
PH0 falls. This guarantees that there is enough time for the address to be decoded and for
/M2SEL and M2B0 to be asserted by the FPI chip if the DMA transfer is to the 1 MHz side of
the system. The bank address must be stored in the DMA bank register at location $C037 before
using DMA.
/DMA is a active-low signal and should be driven with an open-collector driver. The Apple IIGS
provides a pullup for /DMA, but since the pullup is a fairly high value, it is a good idea for an
expansion card that has asserted /DMA to momentarily pull it high for a few nanoseconds when
deasserting it.
Note that there is a minor hardware bug in the Apple IIGS that could cause problems for
developers who are unaware of it. If the CPU is currently pulling an interrupt vector when the
/DMA signal is asserted, and if the DMA address is accessing the language card ($D000-$FFFF)
space in a bank of memory where I/O and language card emulation is enabled (normally banks
$00, $01, $E0 and $E1), DMA reads access ROM rather than RAM. This happens because the
CPU’s Vector Pull (VP) signal is active while the DMA cycle is active. Since most expansion
cards that use DMA are also associated with some corresponding firmware or software driver,
it’s a good idea to disable interrupts prior to doing the DMA transfer, then re-enable interrupts as
soon as possible after the transfer is complete. If interrupts are off too long, AppleTalk shuts
down any connections to file servers because the system does not respond to AppleTalk “tickle”
transactions while interrupts are disabled.
We recommend that the DMA be done with the Apple IIGS running at 1 MHz. If DMA is started
during a 1 MHz cycle (/M2SEL asserted), the system continues to run slow while the /DMA
signal is active.
Avoiding “Bus Fights”
The data bus on the Apple IIGS (and Apple IIe) expansion slots is a multiplexed bus that is used
to carry both CPU and video display data. While PH0 is low, the bus is used to transfer data
from the system RAM to the video display circuitry. When PH0 is high, the bus is available for
CPU data transfers. To avoid potential (or actual) bus fights, it is helpful to avoid driving read
data from an expansion card onto the bus immediately after PH0 rises. Since the video read data
is driven out onto the expansion slots, and expansion card read data is driven in from the slots, it
takes a finite period of time for the bus buffers to turn around. If a card drives data onto the
expansion slot data bus immediately after PH0 rises, there may be a bus fight between the
expansion card trying to drive the bus, and the Apple IIGS (or Apple IIe) bus buffers, which may
not have turned around yet. A similar problem can occur if an expansion card leaves its read
data on the bus too long after PH0 falls.
On the Apple IIGS, the data buffers turn around in 30 nanoseconds or less from the PH0 edges.
Developers can avoid bus fights by simply using 74LS or 74HCT series parts and relying upon
typical delay stackups to delay driving the data bus for approximately 30 nanoseconds. A more