Specifications

Apple II Technical Notes
4 of 6 #68: Tips for I/O Expansion Slot Card Design
PH0
/M2SEL
Safe to
assert or
deassert
PH2
25ns max
35ns min
/NMI,
/IRQ,
/RST,
RDY
60ns min
Figure 2–Control Signal Setup Time
Interrupt Request, Non-Maskable Interrupt, and Reset
The Interrupt Request (/IRQ), the Non-Maskable Interrupt (/NMI) and the Reset (/RST) signals
are all interrupt lines that are sampled by the CPU when the PH2 clock falls. If they are valid 30
nanoseconds before the PH2 clock falls, they are recognized on the following cycle. If this setup
time is not met, they may not be recognized until the second following cycle . Since there can be
up to a 25 nanosecond skew between the PH0 and PH2 clocks, these signals should be valid 60
nanoseconds before PH0 falls if they are to be recognized on the following cycle. Figure 2
shows the correct setup time for these signals.
All three signals are all active-low and must be driven with open-collector drivers.
Note: Interrupt vectors are always pulled from ROM regardless of whether or not the
language card soft-switches have ROM enabled, providing that the I/O shadowing
for banks $00/01 is enabled—which it always is when running Apple IIGS or
Apple II system software.
Direct Memory Access
The Direct Memory Access (/DMA) signal is used to temporarily halt the CPU and allow
expansion cards direct access to the system RAM to transfer data at high speeds. Since the
65C816 is fully static while the PH2 clock is high (unlike the 6502), /DMA may be asserted for
as long as necessary on the Apple IIGS.