Specifications

Developer Technical Support September 1989
Apple IIGS
#68: Tips for I/O Expansion Slot Card Design 3 of 6
Using the Ready Signal
The Ready (RDY) input to the 65C816 is used to prevent a CPU cycle from completing until the
expansion card has accepted the data output or has its input data available.
When the RDY input to a 65C02 or 6502 is held low, the processor continues to output the same
address until RDY is released and the CPU completes the current cycle.
In the Apple IIGS, the 65C816 samples the RDY input when the PH2 clock goes low, and if
RDY is low, the current CPU cycle does not complete and the address continues to be emitted.
However, the bank address is not emitted while the clock is low if RDY is held low. To deal
with this situation, the FPI (Fast Processor Interface) custom IC in the Apple IIGS uses a
transparent latch to capture the bank address from the CPU. The latch is transparent while the
PH2 clock is low and holds the bank address while the PH2 clock is high. If RDY is low, the
CPU emits an invalid bank address, so the FPI holds the latch closed while RDY is low. This
action is normally completely transparent to cards in the Apple IIGS expansion slots, but if an
expansion card asserts RDY while the PH2 clock is low, it is likely to cause the FPI to latch an
invalid bank address, because the latch could close before the bank address from the CPU is
available on the data lines.
To avoid unpredictable results, RDY should only be asserted or deasserted when /M2SEL is low
and when PH0 is high, or when /DEVSEL, /IOSEL or /IOSTRB are active. When /M2SEL,
/DEVSEL, /IOSEL or /IOSTRB are active, you are guaranteed that the 65C816 is running at 1
MHz and is properly synchronized to the 1 MHz side of the system. RDY should be stable at
least 60 nanoseconds before the falling edge of PH0 to allow for about a 25 nanosecond skew
between the PH0 slot clock and the PH2 CPU clock. Figure 2 shows where it is safe to assert or
deassert RDY. Limiting changes to RDY to the time when PH0 is high guarantees that it does
not change while the CPU is outputting the bank address.
The RDY line should be driven with an open-collector driver.