Specifications

Apple II Technical Notes
2 of 6 #68: Tips for I/O Expansion Slot Card Design
accesses to internal I/O or expansion card slots, and accesses to banks $E0 and $E1. Accesses to
any expansion card ROM areas that are set to Internal ROM with the Slot register do not assert
the /M2SEL signal and run at the 2.8 MHz speed rather than the normal 1 MHz expansion card
speed. Also, accesses to the Shadow register ($C035), CYA register ($C036), or DMA bank
register ($C037), and reads from the Slot register ($C02D) or State Register ($C068) run at full
speed since they are done wholly on the fast side of the system.
/M2SEL can be viewed as an extension of the address bus on the expansion slots. When it is
active, it indicates that the CPU is running synchronized with the 1 MHz side of the system and
the address on the address lines is a valid Apple II address in the 128K main or auxiliary memory
space.
The Mega II Bank 0 Signal
The Mega II bank 0 signal (M2B0) provides the least significant bit of the CPU or DMA bank
address to the 1 MHz side of the system. It is normally tri-stated and goes active for 140
nanoseconds, starting 140 nanoseconds after the PH0 clock falls. During the 140 nanosecond
active period, M2B0 will be high whenever the CPU is accessing bank $E1 (with the exceptions
noted previously) or doing a shadowed video write or I/O access in bank $01. Note that M2B0
does not reflect the state of the RAMRD, RAMWRT, ALTZP, 80STORE, or PAGE2 soft switches
that allow access to the auxiliary 64K through bank $00. It only indicates accesses to bank $E1
or shadowed accesses through bank $01.
It is generally safe to latch the state of M2B0 by using the falling edge of the Q3 clock. Even
though M2B0 will be tri-stated at the about the same time as Q3 falls, the turn-off and float time
on M2B0 will generally provide sufficient hold time provided that there is not more than 1 LS
TTL load on M2B0.
PH0
Q3
M2B0
Latch state of M2B0 here
Figure 1–When to Latch State of M2B0
The Apple Video Overlay card uses M2B0 to detect writes to main and auxiliary RAM so that it
can capture writes to the Apple IIGS video display buffers into its on-card display buffer. M2B0
is designed for this sort of thing and isn’t of much use in most other applications. Note that
M2B0 is only available on slot 3.