User`s guide

Pin 27: DMA daisy chain in.
Pin 28: Interrupt daisy chain in.
Pin 29: Non Maskable Interrupt.
Pin 30: Interrupt Request.
Pin 31: Reset.
Pin 32: this is the INHIBIT pin on all machines. This behaves differently on
all three machines: the II and II+ only allow the $D000-$FFFF ROM area to be
inhibited. The IIe allows RAM to be inhibited as well, but has strange
interaction with main and auxiliary memory. The IIgs only allows this signal to
be used if the machine is running in slow mode.
Pin 33: -12V.
Pin 34: -5V.
Pin 35: unused on the II and II+. On the IIe and IIgs, this is the colour
reference signal on slot 7 only. It is unused for other slots in the IIe,
except for slot 1 where it provides a poorly documented facility to disable the
keyboard address decoding. On the original IIgs, slot 3 provides the M2B0
signal (Mega II Bank 0) via this pin and it is unused on other slots. The ROM 3
provides M2B0 for slots 1 to 6.
Pin 36: 7 MHz system clock.
Pin 37: Q3 - Asymmetrical 2 MHz clock.
Pin 38: Phase 1 clock (1.023 MHz).
Pin 39: something called "USER 1" on the II and II+, which can be used to
disable all I/O decoding if a modification is made on the motherboard. On the
IIe, this pin provides the SYNC signal from the micro, which indicates an opcode
fetch. On the IIgs, this pin provides the M2SEL signal, which indicates that a
valid slow memory access is in progress. This pin must be used by IIgs cards
that decode the address without use of the IOSEL, IOSTRB or DEVSEL pins.
Pin 40: Phase 0 clock (1.023 MHz).
Pin 41: Device Select ($C0n0-$C0nF, where n is the slot number plus 8).
Pins 42-49: Data bus D7-D0.
Pin 50: +12V.