Specifications
Table Of Contents
- Title Page
- Table of Contents
- List of Figures
- List of Tables
- 1 Introduction
- 2 Installation
- 3 Navigating the LCD Display Screens
- 3.1 Basic Operating Procedure
- 3.2 Starting Point: The Main LCD Touch Screen
- 3.3 LCD Display Flow Chart
- 3.4 Details of the Exciter Status Screens
- 3.4.1 System Status Screen
- 3.4.2 Transport Stream Status Screen
- 3.4.3 Adaptive Processing Board Status Screen
- 3.4.4 Digital Processing Screens
- 3.4.4.1 Modulator Board Status, Screen 1/2
- 3.4.4.2 ADC and DAC Boards Status, Screen 2/2
- 3.4.4.3 FLO FPGA Status, Summary, Screen 1/5
- 3.4.4.4 FLO FPGA, GPS & Clock Status, Screen 2/5
- 3.4.4.5 FLO FPGA, Transport Stream Status, Screen 3/5
- 3.4.4.6 FLO FPGA, SFN FIFO Status, Screen 4/5
- 3.4.4.7 FLO FPGA, MTI Status, Screen 5/5
- 3.4.5 IF & RF Processing Status Screens
- 3.4.6 System Control Status Screens
- 3.5 Built In Tests
- 3.6 Details of the System Setup Screens
- 3.7 RTAC Operating Procedures, Main Screen.
- 4 Theory of Operation
- 5 Maintenance and Troubleshooting
- 5.1 Exciter Maintenance
- 5.2 Loading Software
- 5.3 Default Settings For DIagnostics Screens
- 5.4 Typical Settings for the More Critical Exciter Setups
- 5.5 Exciter Troubleshooting Flow Charts
- 5.6 General Troubleshooting
- 5.7 System Troubleshooting
- 5.8 Exciter Troubleshooting
- 6 Parts List
- Appendix A Exciter GUI Screen Captures
APEX™ Exciter Incorporating FLO™ Technology
Details of the System Setup Screens Navigating the LCD Display Screens
2604s300.fm
03/08/07 888-2604-001 Page: 3-51
WARNING: Disconnect primary power prior to servicing.
3.6.7.4 FPGA Configure 4/5
FPGASetup4.bmp
Figure 3-43 FPGA Configure 4/5
FPGA Configure 4/5 consists of registers whose values are written immediately to the
FPGA when changed through the GUI.
FPGA re-initialization shall occur automatically after any FPGA Configure 4/5 register is
changed.
The parameters of the FPGA Configure 4/5 screen are as follows.
• Bandwidth: 5MHz / 6MHz / 7MHz / 8MHz
• National Length: Unsigned Decimal, range dependent on bandwidth:
0-245 5MHz, 0-295 6MHz, 0-345 7MHz, 0-395 8MHz
• Pos. Pilot Length: 2 / 6 / 10 / 14 – not bandwidth dependent
• WID: Unsigned Decimal, range 0-15
• LID: Unsigned Decimal, range 0-15
• Superframe Length: Unsigned Decimal integer, displayed only, not user config-
urable
Superframe Length is written to the FPGA register and displayed on the screen. It is
based on the Bandwidth setting as shown in the following Table:
• Frame Length: Unsigned Decimal integer, displayed only, not user configurable –
see below)
Frame Length shall be calculated, written to the FPGA register, and displayed based
on the following formula:
Bandwidth
Superframe
Length
5 MHz 1000
6 MHz 1200
7 MHz 1400
8 MHz 1600